// *********************************************************************************
// Project Name : zkx2024
// Author       : Glqu
// Email        : QGL_MAX@163.com
// Create Time  : 2024-05-02
// File Name    : SRAM_MUX_TOP.v
// Module Name  : sram_mux_top
// Called By    :
// Abstract     :
//
// 
// *********************************************************************************
// Modification History:
// Date         By              Version                 Change Description
// -----------------------------------------------------------------------
// 2024-05-02    Macro           1.0                     Original
//  
// *********************************************************************************
module sram_mux_top(
    input CLK,
    input RST_N,
    wraddr_srammux_bus.srammux w_mux_0,
    wraddr_srammux_bus.srammux w_mux_1,
    wraddr_srammux_bus.srammux w_mux_2,
    wraddr_srammux_bus.srammux w_mux_3,
    wraddr_srammux_bus.srammux w_mux_4,
    wraddr_srammux_bus.srammux w_mux_5,
    wraddr_srammux_bus.srammux w_mux_6,
    wraddr_srammux_bus.srammux w_mux_7,
    wraddr_srammux_bus.srammux w_mux_8,
    wraddr_srammux_bus.srammux w_mux_9,
    wraddr_srammux_bus.srammux w_mux_10,
    wraddr_srammux_bus.srammux w_mux_11,
    wraddr_srammux_bus.srammux w_mux_12,
    wraddr_srammux_bus.srammux w_mux_13,
    wraddr_srammux_bus.srammux w_mux_14,
    wraddr_srammux_bus.srammux w_mux_15,
    wraddr_srammux_bus.srammux w_mux_16,
    wraddr_srammux_bus.srammux w_mux_17,
    wraddr_srammux_bus.srammux w_mux_18,
    wraddr_srammux_bus.srammux w_mux_19,
    wraddr_srammux_bus.srammux w_mux_20,
    wraddr_srammux_bus.srammux w_mux_21,
    wraddr_srammux_bus.srammux w_mux_22,
    wraddr_srammux_bus.srammux w_mux_23,
    wraddr_srammux_bus.srammux w_mux_24,
    wraddr_srammux_bus.srammux w_mux_25,
    wraddr_srammux_bus.srammux w_mux_26,
    wraddr_srammux_bus.srammux w_mux_27,
    wraddr_srammux_bus.srammux w_mux_28,
    wraddr_srammux_bus.srammux w_mux_29,
    wraddr_srammux_bus.srammux w_mux_30,
    wraddr_srammux_bus.srammux w_mux_31,
    wraddr_srammux_bus.srammux w_mux_32,
    wraddr_srammux_bus.srammux w_mux_33,
    wraddr_srammux_bus.srammux w_mux_34,
    wraddr_srammux_bus.srammux w_mux_35,
    wraddr_srammux_bus.srammux w_mux_36,
    wraddr_srammux_bus.srammux w_mux_37,
    wraddr_srammux_bus.srammux w_mux_38,
    wraddr_srammux_bus.srammux w_mux_39,
    wraddr_srammux_bus.srammux w_mux_40,
    wraddr_srammux_bus.srammux w_mux_41,
    wraddr_srammux_bus.srammux w_mux_42,
    wraddr_srammux_bus.srammux w_mux_43,
    wraddr_srammux_bus.srammux w_mux_44,
    wraddr_srammux_bus.srammux w_mux_45,
    wraddr_srammux_bus.srammux w_mux_46,
    wraddr_srammux_bus.srammux w_mux_47,

    rdaddr_srammux_bus.srammux r_mux_0,
    rdaddr_srammux_bus.srammux r_mux_1,
    rdaddr_srammux_bus.srammux r_mux_2,
    rdaddr_srammux_bus.srammux r_mux_3,
    rdaddr_srammux_bus.srammux r_mux_4,
    rdaddr_srammux_bus.srammux r_mux_5,
    rdaddr_srammux_bus.srammux r_mux_6,
    rdaddr_srammux_bus.srammux r_mux_7,
    rdaddr_srammux_bus.srammux r_mux_8,
    rdaddr_srammux_bus.srammux r_mux_9,
    rdaddr_srammux_bus.srammux r_mux_10,
    rdaddr_srammux_bus.srammux r_mux_11,
    rdaddr_srammux_bus.srammux r_mux_12,
    rdaddr_srammux_bus.srammux r_mux_13,
    rdaddr_srammux_bus.srammux r_mux_14,
    rdaddr_srammux_bus.srammux r_mux_15,

    srammux_sram_bus.srammux sram_mux_0,
    srammux_sram_bus.srammux sram_mux_1,
    srammux_sram_bus.srammux sram_mux_2,
    srammux_sram_bus.srammux sram_mux_3,
    srammux_sram_bus.srammux sram_mux_4,
    srammux_sram_bus.srammux sram_mux_5,
    srammux_sram_bus.srammux sram_mux_6,
    srammux_sram_bus.srammux sram_mux_7,
    srammux_sram_bus.srammux sram_mux_8,
    srammux_sram_bus.srammux sram_mux_9,
    srammux_sram_bus.srammux sram_mux_10,
    srammux_sram_bus.srammux sram_mux_11,
    srammux_sram_bus.srammux sram_mux_12,
    srammux_sram_bus.srammux sram_mux_13,
    srammux_sram_bus.srammux sram_mux_14,
    srammux_sram_bus.srammux sram_mux_15

);

logic [4:0] SRAM_NUM_0;
logic [4:0] SRAM_NUM_1;
logic [4:0] SRAM_NUM_2;
logic [4:0] SRAM_NUM_3;
logic [4:0] SRAM_NUM_4;
logic [4:0] SRAM_NUM_5;
logic [4:0] SRAM_NUM_6;
logic [4:0] SRAM_NUM_7;
logic [4:0] SRAM_NUM_8;
logic [4:0] SRAM_NUM_9;
logic [4:0] SRAM_NUM_10;
logic [4:0] SRAM_NUM_11;
logic [4:0] SRAM_NUM_12;
logic [4:0] SRAM_NUM_13;
logic [4:0] SRAM_NUM_14;
logic [4:0] SRAM_NUM_15;
logic [12:0] SRAM_ADDR_0;
logic [12:0] SRAM_ADDR_1;
logic [12:0] SRAM_ADDR_2;
logic [12:0] SRAM_ADDR_3;
logic [12:0] SRAM_ADDR_4;
logic [12:0] SRAM_ADDR_5;
logic [12:0] SRAM_ADDR_6;
logic [12:0] SRAM_ADDR_7;
logic [12:0] SRAM_ADDR_8;
logic [12:0] SRAM_ADDR_9;
logic [12:0] SRAM_ADDR_10;
logic [12:0] SRAM_ADDR_11;
logic [12:0] SRAM_ADDR_12;
logic [12:0] SRAM_ADDR_13;
logic [12:0] SRAM_ADDR_14;
logic [12:0] SRAM_ADDR_15;
logic [12:0] ADDR_O_0;
logic [12:0] ADDR_O_1;
logic [12:0] ADDR_O_2;
logic [12:0] ADDR_O_3;
logic [12:0] ADDR_O_4;
logic [12:0] ADDR_O_5;
logic [12:0] ADDR_O_6;
logic [12:0] ADDR_O_7;
logic [12:0] ADDR_O_8;
logic [12:0] ADDR_O_9;
logic [12:0] ADDR_O_10;
logic [12:0] ADDR_O_11;
logic [12:0] ADDR_O_12;
logic [12:0] ADDR_O_13;
logic [12:0] ADDR_O_14;
logic [12:0] ADDR_O_15;
logic RD_0;
logic RD_1;
logic RD_2;
logic RD_3;
logic RD_4;
logic RD_5;
logic RD_6;
logic RD_7;
logic RD_8;
logic RD_9;
logic RD_10;
logic RD_11;
logic RD_12;
logic RD_13;
logic RD_14;
logic RD_15;

wr_sram_ctrl#(.WR_SRAM_num(16))
            sram_ctrl_u_0(
                .WR_EN_0(w_mux_0.WR_EN),
                .WR_ADDR_0(w_mux_0.WR_ADDR),
                .WR_DATA_0(w_mux_0.WR_DATA),
                .WR_SRAM_NUM_0(w_mux_0.WR_SRAM_NUM),
                .WR_EN_1(w_mux_1.WR_EN),
                .WR_ADDR_1(w_mux_1.WR_ADDR),
                .WR_DATA_1(w_mux_1.WR_DATA),
                .WR_SRAM_NUM_1(w_mux_1.WR_SRAM_NUM),
                .WR_EN_2(w_mux_2.WR_EN),
                .WR_ADDR_2(w_mux_2.WR_ADDR),
                .WR_DATA_2(w_mux_2.WR_DATA),
                .WR_SRAM_NUM_2(w_mux_2.WR_SRAM_NUM),
                .WR_EN_3(w_mux_3.WR_EN),
                .WR_ADDR_3(w_mux_3.WR_ADDR),
                .WR_DATA_3(w_mux_3.WR_DATA),
                .WR_SRAM_NUM_3(w_mux_3.WR_SRAM_NUM),
                .WR_EN_4(w_mux_4.WR_EN),
                .WR_ADDR_4(w_mux_4.WR_ADDR),
                .WR_DATA_4(w_mux_4.WR_DATA),
                .WR_SRAM_NUM_4(w_mux_4.WR_SRAM_NUM),
                .WR_EN_5(w_mux_5.WR_EN),
                .WR_ADDR_5(w_mux_5.WR_ADDR),
                .WR_DATA_5(w_mux_5.WR_DATA),
                .WR_SRAM_NUM_5(w_mux_5.WR_SRAM_NUM),
                .WR_EN_6(w_mux_6.WR_EN),
                .WR_ADDR_6(w_mux_6.WR_ADDR),
                .WR_DATA_6(w_mux_6.WR_DATA),
                .WR_SRAM_NUM_6(w_mux_6.WR_SRAM_NUM),
                .WR_EN_7(w_mux_7.WR_EN),
                .WR_ADDR_7(w_mux_7.WR_ADDR),
                .WR_DATA_7(w_mux_7.WR_DATA),
                .WR_SRAM_NUM_7(w_mux_7.WR_SRAM_NUM),
                .WR_EN_8(w_mux_8.WR_EN),
                .WR_ADDR_8(w_mux_8.WR_ADDR),
                .WR_DATA_8(w_mux_8.WR_DATA),
                .WR_SRAM_NUM_8(w_mux_8.WR_SRAM_NUM),
                .WR_EN_9(w_mux_9.WR_EN),
                .WR_ADDR_9(w_mux_9.WR_ADDR),
                .WR_DATA_9(w_mux_9.WR_DATA),
                .WR_SRAM_NUM_9(w_mux_9.WR_SRAM_NUM),
                .WR_EN_10(w_mux_10.WR_EN),
                .WR_ADDR_10(w_mux_10.WR_ADDR),
                .WR_DATA_10(w_mux_10.WR_DATA),
                .WR_SRAM_NUM_10(w_mux_10.WR_SRAM_NUM),
                .WR_EN_11(w_mux_11.WR_EN),
                .WR_ADDR_11(w_mux_11.WR_ADDR),
                .WR_DATA_11(w_mux_11.WR_DATA),
                .WR_SRAM_NUM_11(w_mux_11.WR_SRAM_NUM),
                .WR_EN_12(w_mux_12.WR_EN),
                .WR_ADDR_12(w_mux_12.WR_ADDR),
                .WR_DATA_12(w_mux_12.WR_DATA),
                .WR_SRAM_NUM_12(w_mux_12.WR_SRAM_NUM),
                .WR_EN_13(w_mux_13.WR_EN),
                .WR_ADDR_13(w_mux_13.WR_ADDR),
                .WR_DATA_13(w_mux_13.WR_DATA),
                .WR_SRAM_NUM_13(w_mux_13.WR_SRAM_NUM),
                .WR_EN_14(w_mux_14.WR_EN),
                .WR_ADDR_14(w_mux_14.WR_ADDR),
                .WR_DATA_14(w_mux_14.WR_DATA),
                .WR_SRAM_NUM_14(w_mux_14.WR_SRAM_NUM),
                .WR_EN_15(w_mux_15.WR_EN),
                .WR_ADDR_15(w_mux_15.WR_ADDR),
                .WR_DATA_15(w_mux_15.WR_DATA),
                .WR_SRAM_NUM_15(w_mux_15.WR_SRAM_NUM),
                .WR_EN_16(w_mux_16.WR_EN),
                .WR_ADDR_16(w_mux_16.WR_ADDR),
                .WR_DATA_16(w_mux_16.WR_DATA),
                .WR_SRAM_NUM_16(w_mux_16.WR_SRAM_NUM),
                .WR_EN_17(w_mux_17.WR_EN),
                .WR_ADDR_17(w_mux_17.WR_ADDR),
                .WR_DATA_17(w_mux_17.WR_DATA),
                .WR_SRAM_NUM_17(w_mux_17.WR_SRAM_NUM),
                .WR_EN_18(w_mux_18.WR_EN),
                .WR_ADDR_18(w_mux_18.WR_ADDR),
                .WR_DATA_18(w_mux_18.WR_DATA),
                .WR_SRAM_NUM_18(w_mux_18.WR_SRAM_NUM),
                .WR_EN_19(w_mux_19.WR_EN),
                .WR_ADDR_19(w_mux_19.WR_ADDR),
                .WR_DATA_19(w_mux_19.WR_DATA),
                .WR_SRAM_NUM_19(w_mux_19.WR_SRAM_NUM),
                .WR_EN_20(w_mux_20.WR_EN),
                .WR_ADDR_20(w_mux_20.WR_ADDR),
                .WR_DATA_20(w_mux_20.WR_DATA),
                .WR_SRAM_NUM_20(w_mux_20.WR_SRAM_NUM),
                .WR_EN_21(w_mux_21.WR_EN),
                .WR_ADDR_21(w_mux_21.WR_ADDR),
                .WR_DATA_21(w_mux_21.WR_DATA),
                .WR_SRAM_NUM_21(w_mux_21.WR_SRAM_NUM),
                .WR_EN_22(w_mux_22.WR_EN),
                .WR_ADDR_22(w_mux_22.WR_ADDR),
                .WR_DATA_22(w_mux_22.WR_DATA),
                .WR_SRAM_NUM_22(w_mux_22.WR_SRAM_NUM),
                .WR_EN_23(w_mux_23.WR_EN),
                .WR_ADDR_23(w_mux_23.WR_ADDR),
                .WR_DATA_23(w_mux_23.WR_DATA),
                .WR_SRAM_NUM_23(w_mux_23.WR_SRAM_NUM),
                .WR_EN_24(w_mux_24.WR_EN),
                .WR_ADDR_24(w_mux_24.WR_ADDR),
                .WR_DATA_24(w_mux_24.WR_DATA),
                .WR_SRAM_NUM_24(w_mux_24.WR_SRAM_NUM),
                .WR_EN_25(w_mux_25.WR_EN),
                .WR_ADDR_25(w_mux_25.WR_ADDR),
                .WR_DATA_25(w_mux_25.WR_DATA),
                .WR_SRAM_NUM_25(w_mux_25.WR_SRAM_NUM),
                .WR_EN_26(w_mux_26.WR_EN),
                .WR_ADDR_26(w_mux_26.WR_ADDR),
                .WR_DATA_26(w_mux_26.WR_DATA),
                .WR_SRAM_NUM_26(w_mux_26.WR_SRAM_NUM),
                .WR_EN_27(w_mux_27.WR_EN),
                .WR_ADDR_27(w_mux_27.WR_ADDR),
                .WR_DATA_27(w_mux_27.WR_DATA),
                .WR_SRAM_NUM_27(w_mux_27.WR_SRAM_NUM),
                .WR_EN_28(w_mux_28.WR_EN),
                .WR_ADDR_28(w_mux_28.WR_ADDR),
                .WR_DATA_28(w_mux_28.WR_DATA),
                .WR_SRAM_NUM_28(w_mux_28.WR_SRAM_NUM),
                .WR_EN_29(w_mux_29.WR_EN),
                .WR_ADDR_29(w_mux_29.WR_ADDR),
                .WR_DATA_29(w_mux_29.WR_DATA),
                .WR_SRAM_NUM_29(w_mux_29.WR_SRAM_NUM),
                .WR_EN_30(w_mux_30.WR_EN),
                .WR_ADDR_30(w_mux_30.WR_ADDR),
                .WR_DATA_30(w_mux_30.WR_DATA),
                .WR_SRAM_NUM_30(w_mux_30.WR_SRAM_NUM),
                .WR_EN_31(w_mux_31.WR_EN),
                .WR_ADDR_31(w_mux_31.WR_ADDR),
                .WR_DATA_31(w_mux_31.WR_DATA),
                .WR_SRAM_NUM_31(w_mux_31.WR_SRAM_NUM),
                .WR_EN_32(w_mux_32.WR_EN),
                .WR_ADDR_32(w_mux_32.WR_ADDR),
                .WR_DATA_32(w_mux_32.WR_DATA),
                .WR_SRAM_NUM_32(w_mux_32.WR_SRAM_NUM),
                .WR_EN_33(w_mux_33.WR_EN),
                .WR_ADDR_33(w_mux_33.WR_ADDR),
                .WR_DATA_33(w_mux_33.WR_DATA),
                .WR_SRAM_NUM_33(w_mux_33.WR_SRAM_NUM),
                .WR_EN_34(w_mux_34.WR_EN),
                .WR_ADDR_34(w_mux_34.WR_ADDR),
                .WR_DATA_34(w_mux_34.WR_DATA),
                .WR_SRAM_NUM_34(w_mux_34.WR_SRAM_NUM),
                .WR_EN_35(w_mux_35.WR_EN),
                .WR_ADDR_35(w_mux_35.WR_ADDR),
                .WR_DATA_35(w_mux_35.WR_DATA),
                .WR_SRAM_NUM_35(w_mux_35.WR_SRAM_NUM),
                .WR_EN_36(w_mux_36.WR_EN),
                .WR_ADDR_36(w_mux_36.WR_ADDR),
                .WR_DATA_36(w_mux_36.WR_DATA),
                .WR_SRAM_NUM_36(w_mux_36.WR_SRAM_NUM),
                .WR_EN_37(w_mux_37.WR_EN),
                .WR_ADDR_37(w_mux_37.WR_ADDR),
                .WR_DATA_37(w_mux_37.WR_DATA),
                .WR_SRAM_NUM_37(w_mux_37.WR_SRAM_NUM),
                .WR_EN_38(w_mux_38.WR_EN),
                .WR_ADDR_38(w_mux_38.WR_ADDR),
                .WR_DATA_38(w_mux_38.WR_DATA),
                .WR_SRAM_NUM_38(w_mux_38.WR_SRAM_NUM),
                .WR_EN_39(w_mux_39.WR_EN),
                .WR_ADDR_39(w_mux_39.WR_ADDR),
                .WR_DATA_39(w_mux_39.WR_DATA),
                .WR_SRAM_NUM_39(w_mux_39.WR_SRAM_NUM),
                .WR_EN_40(w_mux_40.WR_EN),
                .WR_ADDR_40(w_mux_40.WR_ADDR),
                .WR_DATA_40(w_mux_40.WR_DATA),
                .WR_SRAM_NUM_40(w_mux_40.WR_SRAM_NUM),
                .WR_EN_41(w_mux_41.WR_EN),
                .WR_ADDR_41(w_mux_41.WR_ADDR),
                .WR_DATA_41(w_mux_41.WR_DATA),
                .WR_SRAM_NUM_41(w_mux_41.WR_SRAM_NUM),
                .WR_EN_42(w_mux_42.WR_EN),
                .WR_ADDR_42(w_mux_42.WR_ADDR),
                .WR_DATA_42(w_mux_42.WR_DATA),
                .WR_SRAM_NUM_42(w_mux_42.WR_SRAM_NUM),
                .WR_EN_43(w_mux_43.WR_EN),
                .WR_ADDR_43(w_mux_43.WR_ADDR),
                .WR_DATA_43(w_mux_43.WR_DATA),
                .WR_SRAM_NUM_43(w_mux_43.WR_SRAM_NUM),
                .WR_EN_44(w_mux_44.WR_EN),
                .WR_ADDR_44(w_mux_44.WR_ADDR),
                .WR_DATA_44(w_mux_44.WR_DATA),
                .WR_SRAM_NUM_44(w_mux_44.WR_SRAM_NUM),
                .WR_EN_45(w_mux_45.WR_EN),
                .WR_ADDR_45(w_mux_45.WR_ADDR),
                .WR_DATA_45(w_mux_45.WR_DATA),
                .WR_SRAM_NUM_45(w_mux_45.WR_SRAM_NUM),
                .WR_EN_46(w_mux_46.WR_EN),
                .WR_ADDR_46(w_mux_46.WR_ADDR),
                .WR_DATA_46(w_mux_46.WR_DATA),
                .WR_SRAM_NUM_46(w_mux_46.WR_SRAM_NUM),
                .WR_EN_47(w_mux_47.WR_EN),
                .WR_ADDR_47(w_mux_47.WR_ADDR),
                .WR_DATA_47(w_mux_47.WR_DATA),
                .WR_SRAM_NUM_47(w_mux_47.WR_SRAM_NUM),
                .W_DATA(sram_mux_0.W_DATA),
                .W_ADDR(sram_mux_0.W_ADDR),
                .WR(sram_mux_0.WR)
            );
wr_sram_ctrl#(.WR_SRAM_num(17))
            sram_ctrl_u_1(
                .WR_EN_0(w_mux_0.WR_EN),
                .WR_ADDR_0(w_mux_0.WR_ADDR),
                .WR_DATA_0(w_mux_0.WR_DATA),
                .WR_SRAM_NUM_0(w_mux_0.WR_SRAM_NUM),
                .WR_EN_1(w_mux_1.WR_EN),
                .WR_ADDR_1(w_mux_1.WR_ADDR),
                .WR_DATA_1(w_mux_1.WR_DATA),
                .WR_SRAM_NUM_1(w_mux_1.WR_SRAM_NUM),
                .WR_EN_2(w_mux_2.WR_EN),
                .WR_ADDR_2(w_mux_2.WR_ADDR),
                .WR_DATA_2(w_mux_2.WR_DATA),
                .WR_SRAM_NUM_2(w_mux_2.WR_SRAM_NUM),
                .WR_EN_3(w_mux_3.WR_EN),
                .WR_ADDR_3(w_mux_3.WR_ADDR),
                .WR_DATA_3(w_mux_3.WR_DATA),
                .WR_SRAM_NUM_3(w_mux_3.WR_SRAM_NUM),
                .WR_EN_4(w_mux_4.WR_EN),
                .WR_ADDR_4(w_mux_4.WR_ADDR),
                .WR_DATA_4(w_mux_4.WR_DATA),
                .WR_SRAM_NUM_4(w_mux_4.WR_SRAM_NUM),
                .WR_EN_5(w_mux_5.WR_EN),
                .WR_ADDR_5(w_mux_5.WR_ADDR),
                .WR_DATA_5(w_mux_5.WR_DATA),
                .WR_SRAM_NUM_5(w_mux_5.WR_SRAM_NUM),
                .WR_EN_6(w_mux_6.WR_EN),
                .WR_ADDR_6(w_mux_6.WR_ADDR),
                .WR_DATA_6(w_mux_6.WR_DATA),
                .WR_SRAM_NUM_6(w_mux_6.WR_SRAM_NUM),
                .WR_EN_7(w_mux_7.WR_EN),
                .WR_ADDR_7(w_mux_7.WR_ADDR),
                .WR_DATA_7(w_mux_7.WR_DATA),
                .WR_SRAM_NUM_7(w_mux_7.WR_SRAM_NUM),
                .WR_EN_8(w_mux_8.WR_EN),
                .WR_ADDR_8(w_mux_8.WR_ADDR),
                .WR_DATA_8(w_mux_8.WR_DATA),
                .WR_SRAM_NUM_8(w_mux_8.WR_SRAM_NUM),
                .WR_EN_9(w_mux_9.WR_EN),
                .WR_ADDR_9(w_mux_9.WR_ADDR),
                .WR_DATA_9(w_mux_9.WR_DATA),
                .WR_SRAM_NUM_9(w_mux_9.WR_SRAM_NUM),
                .WR_EN_10(w_mux_10.WR_EN),
                .WR_ADDR_10(w_mux_10.WR_ADDR),
                .WR_DATA_10(w_mux_10.WR_DATA),
                .WR_SRAM_NUM_10(w_mux_10.WR_SRAM_NUM),
                .WR_EN_11(w_mux_11.WR_EN),
                .WR_ADDR_11(w_mux_11.WR_ADDR),
                .WR_DATA_11(w_mux_11.WR_DATA),
                .WR_SRAM_NUM_11(w_mux_11.WR_SRAM_NUM),
                .WR_EN_12(w_mux_12.WR_EN),
                .WR_ADDR_12(w_mux_12.WR_ADDR),
                .WR_DATA_12(w_mux_12.WR_DATA),
                .WR_SRAM_NUM_12(w_mux_12.WR_SRAM_NUM),
                .WR_EN_13(w_mux_13.WR_EN),
                .WR_ADDR_13(w_mux_13.WR_ADDR),
                .WR_DATA_13(w_mux_13.WR_DATA),
                .WR_SRAM_NUM_13(w_mux_13.WR_SRAM_NUM),
                .WR_EN_14(w_mux_14.WR_EN),
                .WR_ADDR_14(w_mux_14.WR_ADDR),
                .WR_DATA_14(w_mux_14.WR_DATA),
                .WR_SRAM_NUM_14(w_mux_14.WR_SRAM_NUM),
                .WR_EN_15(w_mux_15.WR_EN),
                .WR_ADDR_15(w_mux_15.WR_ADDR),
                .WR_DATA_15(w_mux_15.WR_DATA),
                .WR_SRAM_NUM_15(w_mux_15.WR_SRAM_NUM),
                .WR_EN_16(w_mux_16.WR_EN),
                .WR_ADDR_16(w_mux_16.WR_ADDR),
                .WR_DATA_16(w_mux_16.WR_DATA),
                .WR_SRAM_NUM_16(w_mux_16.WR_SRAM_NUM),
                .WR_EN_17(w_mux_17.WR_EN),
                .WR_ADDR_17(w_mux_17.WR_ADDR),
                .WR_DATA_17(w_mux_17.WR_DATA),
                .WR_SRAM_NUM_17(w_mux_17.WR_SRAM_NUM),
                .WR_EN_18(w_mux_18.WR_EN),
                .WR_ADDR_18(w_mux_18.WR_ADDR),
                .WR_DATA_18(w_mux_18.WR_DATA),
                .WR_SRAM_NUM_18(w_mux_18.WR_SRAM_NUM),
                .WR_EN_19(w_mux_19.WR_EN),
                .WR_ADDR_19(w_mux_19.WR_ADDR),
                .WR_DATA_19(w_mux_19.WR_DATA),
                .WR_SRAM_NUM_19(w_mux_19.WR_SRAM_NUM),
                .WR_EN_20(w_mux_20.WR_EN),
                .WR_ADDR_20(w_mux_20.WR_ADDR),
                .WR_DATA_20(w_mux_20.WR_DATA),
                .WR_SRAM_NUM_20(w_mux_20.WR_SRAM_NUM),
                .WR_EN_21(w_mux_21.WR_EN),
                .WR_ADDR_21(w_mux_21.WR_ADDR),
                .WR_DATA_21(w_mux_21.WR_DATA),
                .WR_SRAM_NUM_21(w_mux_21.WR_SRAM_NUM),
                .WR_EN_22(w_mux_22.WR_EN),
                .WR_ADDR_22(w_mux_22.WR_ADDR),
                .WR_DATA_22(w_mux_22.WR_DATA),
                .WR_SRAM_NUM_22(w_mux_22.WR_SRAM_NUM),
                .WR_EN_23(w_mux_23.WR_EN),
                .WR_ADDR_23(w_mux_23.WR_ADDR),
                .WR_DATA_23(w_mux_23.WR_DATA),
                .WR_SRAM_NUM_23(w_mux_23.WR_SRAM_NUM),
                .WR_EN_24(w_mux_24.WR_EN),
                .WR_ADDR_24(w_mux_24.WR_ADDR),
                .WR_DATA_24(w_mux_24.WR_DATA),
                .WR_SRAM_NUM_24(w_mux_24.WR_SRAM_NUM),
                .WR_EN_25(w_mux_25.WR_EN),
                .WR_ADDR_25(w_mux_25.WR_ADDR),
                .WR_DATA_25(w_mux_25.WR_DATA),
                .WR_SRAM_NUM_25(w_mux_25.WR_SRAM_NUM),
                .WR_EN_26(w_mux_26.WR_EN),
                .WR_ADDR_26(w_mux_26.WR_ADDR),
                .WR_DATA_26(w_mux_26.WR_DATA),
                .WR_SRAM_NUM_26(w_mux_26.WR_SRAM_NUM),
                .WR_EN_27(w_mux_27.WR_EN),
                .WR_ADDR_27(w_mux_27.WR_ADDR),
                .WR_DATA_27(w_mux_27.WR_DATA),
                .WR_SRAM_NUM_27(w_mux_27.WR_SRAM_NUM),
                .WR_EN_28(w_mux_28.WR_EN),
                .WR_ADDR_28(w_mux_28.WR_ADDR),
                .WR_DATA_28(w_mux_28.WR_DATA),
                .WR_SRAM_NUM_28(w_mux_28.WR_SRAM_NUM),
                .WR_EN_29(w_mux_29.WR_EN),
                .WR_ADDR_29(w_mux_29.WR_ADDR),
                .WR_DATA_29(w_mux_29.WR_DATA),
                .WR_SRAM_NUM_29(w_mux_29.WR_SRAM_NUM),
                .WR_EN_30(w_mux_30.WR_EN),
                .WR_ADDR_30(w_mux_30.WR_ADDR),
                .WR_DATA_30(w_mux_30.WR_DATA),
                .WR_SRAM_NUM_30(w_mux_30.WR_SRAM_NUM),
                .WR_EN_31(w_mux_31.WR_EN),
                .WR_ADDR_31(w_mux_31.WR_ADDR),
                .WR_DATA_31(w_mux_31.WR_DATA),
                .WR_SRAM_NUM_31(w_mux_31.WR_SRAM_NUM),
                .WR_EN_32(w_mux_32.WR_EN),
                .WR_ADDR_32(w_mux_32.WR_ADDR),
                .WR_DATA_32(w_mux_32.WR_DATA),
                .WR_SRAM_NUM_32(w_mux_32.WR_SRAM_NUM),
                .WR_EN_33(w_mux_33.WR_EN),
                .WR_ADDR_33(w_mux_33.WR_ADDR),
                .WR_DATA_33(w_mux_33.WR_DATA),
                .WR_SRAM_NUM_33(w_mux_33.WR_SRAM_NUM),
                .WR_EN_34(w_mux_34.WR_EN),
                .WR_ADDR_34(w_mux_34.WR_ADDR),
                .WR_DATA_34(w_mux_34.WR_DATA),
                .WR_SRAM_NUM_34(w_mux_34.WR_SRAM_NUM),
                .WR_EN_35(w_mux_35.WR_EN),
                .WR_ADDR_35(w_mux_35.WR_ADDR),
                .WR_DATA_35(w_mux_35.WR_DATA),
                .WR_SRAM_NUM_35(w_mux_35.WR_SRAM_NUM),
                .WR_EN_36(w_mux_36.WR_EN),
                .WR_ADDR_36(w_mux_36.WR_ADDR),
                .WR_DATA_36(w_mux_36.WR_DATA),
                .WR_SRAM_NUM_36(w_mux_36.WR_SRAM_NUM),
                .WR_EN_37(w_mux_37.WR_EN),
                .WR_ADDR_37(w_mux_37.WR_ADDR),
                .WR_DATA_37(w_mux_37.WR_DATA),
                .WR_SRAM_NUM_37(w_mux_37.WR_SRAM_NUM),
                .WR_EN_38(w_mux_38.WR_EN),
                .WR_ADDR_38(w_mux_38.WR_ADDR),
                .WR_DATA_38(w_mux_38.WR_DATA),
                .WR_SRAM_NUM_38(w_mux_38.WR_SRAM_NUM),
                .WR_EN_39(w_mux_39.WR_EN),
                .WR_ADDR_39(w_mux_39.WR_ADDR),
                .WR_DATA_39(w_mux_39.WR_DATA),
                .WR_SRAM_NUM_39(w_mux_39.WR_SRAM_NUM),
                .WR_EN_40(w_mux_40.WR_EN),
                .WR_ADDR_40(w_mux_40.WR_ADDR),
                .WR_DATA_40(w_mux_40.WR_DATA),
                .WR_SRAM_NUM_40(w_mux_40.WR_SRAM_NUM),
                .WR_EN_41(w_mux_41.WR_EN),
                .WR_ADDR_41(w_mux_41.WR_ADDR),
                .WR_DATA_41(w_mux_41.WR_DATA),
                .WR_SRAM_NUM_41(w_mux_41.WR_SRAM_NUM),
                .WR_EN_42(w_mux_42.WR_EN),
                .WR_ADDR_42(w_mux_42.WR_ADDR),
                .WR_DATA_42(w_mux_42.WR_DATA),
                .WR_SRAM_NUM_42(w_mux_42.WR_SRAM_NUM),
                .WR_EN_43(w_mux_43.WR_EN),
                .WR_ADDR_43(w_mux_43.WR_ADDR),
                .WR_DATA_43(w_mux_43.WR_DATA),
                .WR_SRAM_NUM_43(w_mux_43.WR_SRAM_NUM),
                .WR_EN_44(w_mux_44.WR_EN),
                .WR_ADDR_44(w_mux_44.WR_ADDR),
                .WR_DATA_44(w_mux_44.WR_DATA),
                .WR_SRAM_NUM_44(w_mux_44.WR_SRAM_NUM),
                .WR_EN_45(w_mux_45.WR_EN),
                .WR_ADDR_45(w_mux_45.WR_ADDR),
                .WR_DATA_45(w_mux_45.WR_DATA),
                .WR_SRAM_NUM_45(w_mux_45.WR_SRAM_NUM),
                .WR_EN_46(w_mux_46.WR_EN),
                .WR_ADDR_46(w_mux_46.WR_ADDR),
                .WR_DATA_46(w_mux_46.WR_DATA),
                .WR_SRAM_NUM_46(w_mux_46.WR_SRAM_NUM),
                .WR_EN_47(w_mux_47.WR_EN),
                .WR_ADDR_47(w_mux_47.WR_ADDR),
                .WR_DATA_47(w_mux_47.WR_DATA),
                .WR_SRAM_NUM_47(w_mux_47.WR_SRAM_NUM),
                .W_DATA(sram_mux_1.W_DATA),
                .W_ADDR(sram_mux_1.W_ADDR),
                .WR(sram_mux_1.WR)
            );
            
            wr_sram_ctrl#(.WR_SRAM_num(18))
            sram_ctrl_u_2(
                .WR_EN_0(w_mux_0.WR_EN),
                .WR_ADDR_0(w_mux_0.WR_ADDR),
                .WR_DATA_0(w_mux_0.WR_DATA),
                .WR_SRAM_NUM_0(w_mux_0.WR_SRAM_NUM),
                .WR_EN_1(w_mux_1.WR_EN),
                .WR_ADDR_1(w_mux_1.WR_ADDR),
                .WR_DATA_1(w_mux_1.WR_DATA),
                .WR_SRAM_NUM_1(w_mux_1.WR_SRAM_NUM),
                .WR_EN_2(w_mux_2.WR_EN),
                .WR_ADDR_2(w_mux_2.WR_ADDR),
                .WR_DATA_2(w_mux_2.WR_DATA),
                .WR_SRAM_NUM_2(w_mux_2.WR_SRAM_NUM),
                .WR_EN_3(w_mux_3.WR_EN),
                .WR_ADDR_3(w_mux_3.WR_ADDR),
                .WR_DATA_3(w_mux_3.WR_DATA),
                .WR_SRAM_NUM_3(w_mux_3.WR_SRAM_NUM),
                .WR_EN_4(w_mux_4.WR_EN),
                .WR_ADDR_4(w_mux_4.WR_ADDR),
                .WR_DATA_4(w_mux_4.WR_DATA),
                .WR_SRAM_NUM_4(w_mux_4.WR_SRAM_NUM),
                .WR_EN_5(w_mux_5.WR_EN),
                .WR_ADDR_5(w_mux_5.WR_ADDR),
                .WR_DATA_5(w_mux_5.WR_DATA),
                .WR_SRAM_NUM_5(w_mux_5.WR_SRAM_NUM),
                .WR_EN_6(w_mux_6.WR_EN),
                .WR_ADDR_6(w_mux_6.WR_ADDR),
                .WR_DATA_6(w_mux_6.WR_DATA),
                .WR_SRAM_NUM_6(w_mux_6.WR_SRAM_NUM),
                .WR_EN_7(w_mux_7.WR_EN),
                .WR_ADDR_7(w_mux_7.WR_ADDR),
                .WR_DATA_7(w_mux_7.WR_DATA),
                .WR_SRAM_NUM_7(w_mux_7.WR_SRAM_NUM),
                .WR_EN_8(w_mux_8.WR_EN),
                .WR_ADDR_8(w_mux_8.WR_ADDR),
                .WR_DATA_8(w_mux_8.WR_DATA),
                .WR_SRAM_NUM_8(w_mux_8.WR_SRAM_NUM),
                .WR_EN_9(w_mux_9.WR_EN),
                .WR_ADDR_9(w_mux_9.WR_ADDR),
                .WR_DATA_9(w_mux_9.WR_DATA),
                .WR_SRAM_NUM_9(w_mux_9.WR_SRAM_NUM),
                .WR_EN_10(w_mux_10.WR_EN),
                .WR_ADDR_10(w_mux_10.WR_ADDR),
                .WR_DATA_10(w_mux_10.WR_DATA),
                .WR_SRAM_NUM_10(w_mux_10.WR_SRAM_NUM),
                .WR_EN_11(w_mux_11.WR_EN),
                .WR_ADDR_11(w_mux_11.WR_ADDR),
                .WR_DATA_11(w_mux_11.WR_DATA),
                .WR_SRAM_NUM_11(w_mux_11.WR_SRAM_NUM),
                .WR_EN_12(w_mux_12.WR_EN),
                .WR_ADDR_12(w_mux_12.WR_ADDR),
                .WR_DATA_12(w_mux_12.WR_DATA),
                .WR_SRAM_NUM_12(w_mux_12.WR_SRAM_NUM),
                .WR_EN_13(w_mux_13.WR_EN),
                .WR_ADDR_13(w_mux_13.WR_ADDR),
                .WR_DATA_13(w_mux_13.WR_DATA),
                .WR_SRAM_NUM_13(w_mux_13.WR_SRAM_NUM),
                .WR_EN_14(w_mux_14.WR_EN),
                .WR_ADDR_14(w_mux_14.WR_ADDR),
                .WR_DATA_14(w_mux_14.WR_DATA),
                .WR_SRAM_NUM_14(w_mux_14.WR_SRAM_NUM),
                .WR_EN_15(w_mux_15.WR_EN),
                .WR_ADDR_15(w_mux_15.WR_ADDR),
                .WR_DATA_15(w_mux_15.WR_DATA),
                .WR_SRAM_NUM_15(w_mux_15.WR_SRAM_NUM),
                .WR_EN_16(w_mux_16.WR_EN),
                .WR_ADDR_16(w_mux_16.WR_ADDR),
                .WR_DATA_16(w_mux_16.WR_DATA),
                .WR_SRAM_NUM_16(w_mux_16.WR_SRAM_NUM),
                .WR_EN_17(w_mux_17.WR_EN),
                .WR_ADDR_17(w_mux_17.WR_ADDR),
                .WR_DATA_17(w_mux_17.WR_DATA),
                .WR_SRAM_NUM_17(w_mux_17.WR_SRAM_NUM),
                .WR_EN_18(w_mux_18.WR_EN),
                .WR_ADDR_18(w_mux_18.WR_ADDR),
                .WR_DATA_18(w_mux_18.WR_DATA),
                .WR_SRAM_NUM_18(w_mux_18.WR_SRAM_NUM),
                .WR_EN_19(w_mux_19.WR_EN),
                .WR_ADDR_19(w_mux_19.WR_ADDR),
                .WR_DATA_19(w_mux_19.WR_DATA),
                .WR_SRAM_NUM_19(w_mux_19.WR_SRAM_NUM),
                .WR_EN_20(w_mux_20.WR_EN),
                .WR_ADDR_20(w_mux_20.WR_ADDR),
                .WR_DATA_20(w_mux_20.WR_DATA),
                .WR_SRAM_NUM_20(w_mux_20.WR_SRAM_NUM),
                .WR_EN_21(w_mux_21.WR_EN),
                .WR_ADDR_21(w_mux_21.WR_ADDR),
                .WR_DATA_21(w_mux_21.WR_DATA),
                .WR_SRAM_NUM_21(w_mux_21.WR_SRAM_NUM),
                .WR_EN_22(w_mux_22.WR_EN),
                .WR_ADDR_22(w_mux_22.WR_ADDR),
                .WR_DATA_22(w_mux_22.WR_DATA),
                .WR_SRAM_NUM_22(w_mux_22.WR_SRAM_NUM),
                .WR_EN_23(w_mux_23.WR_EN),
                .WR_ADDR_23(w_mux_23.WR_ADDR),
                .WR_DATA_23(w_mux_23.WR_DATA),
                .WR_SRAM_NUM_23(w_mux_23.WR_SRAM_NUM),
                .WR_EN_24(w_mux_24.WR_EN),
                .WR_ADDR_24(w_mux_24.WR_ADDR),
                .WR_DATA_24(w_mux_24.WR_DATA),
                .WR_SRAM_NUM_24(w_mux_24.WR_SRAM_NUM),
                .WR_EN_25(w_mux_25.WR_EN),
                .WR_ADDR_25(w_mux_25.WR_ADDR),
                .WR_DATA_25(w_mux_25.WR_DATA),
                .WR_SRAM_NUM_25(w_mux_25.WR_SRAM_NUM),
                .WR_EN_26(w_mux_26.WR_EN),
                .WR_ADDR_26(w_mux_26.WR_ADDR),
                .WR_DATA_26(w_mux_26.WR_DATA),
                .WR_SRAM_NUM_26(w_mux_26.WR_SRAM_NUM),
                .WR_EN_27(w_mux_27.WR_EN),
                .WR_ADDR_27(w_mux_27.WR_ADDR),
                .WR_DATA_27(w_mux_27.WR_DATA),
                .WR_SRAM_NUM_27(w_mux_27.WR_SRAM_NUM),
                .WR_EN_28(w_mux_28.WR_EN),
                .WR_ADDR_28(w_mux_28.WR_ADDR),
                .WR_DATA_28(w_mux_28.WR_DATA),
                .WR_SRAM_NUM_28(w_mux_28.WR_SRAM_NUM),
                .WR_EN_29(w_mux_29.WR_EN),
                .WR_ADDR_29(w_mux_29.WR_ADDR),
                .WR_DATA_29(w_mux_29.WR_DATA),
                .WR_SRAM_NUM_29(w_mux_29.WR_SRAM_NUM),
                .WR_EN_30(w_mux_30.WR_EN),
                .WR_ADDR_30(w_mux_30.WR_ADDR),
                .WR_DATA_30(w_mux_30.WR_DATA),
                .WR_SRAM_NUM_30(w_mux_30.WR_SRAM_NUM),
                .WR_EN_31(w_mux_31.WR_EN),
                .WR_ADDR_31(w_mux_31.WR_ADDR),
                .WR_DATA_31(w_mux_31.WR_DATA),
                .WR_SRAM_NUM_31(w_mux_31.WR_SRAM_NUM),
                .WR_EN_32(w_mux_32.WR_EN),
                .WR_ADDR_32(w_mux_32.WR_ADDR),
                .WR_DATA_32(w_mux_32.WR_DATA),
                .WR_SRAM_NUM_32(w_mux_32.WR_SRAM_NUM),
                .WR_EN_33(w_mux_33.WR_EN),
                .WR_ADDR_33(w_mux_33.WR_ADDR),
                .WR_DATA_33(w_mux_33.WR_DATA),
                .WR_SRAM_NUM_33(w_mux_33.WR_SRAM_NUM),
                .WR_EN_34(w_mux_34.WR_EN),
                .WR_ADDR_34(w_mux_34.WR_ADDR),
                .WR_DATA_34(w_mux_34.WR_DATA),
                .WR_SRAM_NUM_34(w_mux_34.WR_SRAM_NUM),
                .WR_EN_35(w_mux_35.WR_EN),
                .WR_ADDR_35(w_mux_35.WR_ADDR),
                .WR_DATA_35(w_mux_35.WR_DATA),
                .WR_SRAM_NUM_35(w_mux_35.WR_SRAM_NUM),
                .WR_EN_36(w_mux_36.WR_EN),
                .WR_ADDR_36(w_mux_36.WR_ADDR),
                .WR_DATA_36(w_mux_36.WR_DATA),
                .WR_SRAM_NUM_36(w_mux_36.WR_SRAM_NUM),
                .WR_EN_37(w_mux_37.WR_EN),
                .WR_ADDR_37(w_mux_37.WR_ADDR),
                .WR_DATA_37(w_mux_37.WR_DATA),
                .WR_SRAM_NUM_37(w_mux_37.WR_SRAM_NUM),
                .WR_EN_38(w_mux_38.WR_EN),
                .WR_ADDR_38(w_mux_38.WR_ADDR),
                .WR_DATA_38(w_mux_38.WR_DATA),
                .WR_SRAM_NUM_38(w_mux_38.WR_SRAM_NUM),
                .WR_EN_39(w_mux_39.WR_EN),
                .WR_ADDR_39(w_mux_39.WR_ADDR),
                .WR_DATA_39(w_mux_39.WR_DATA),
                .WR_SRAM_NUM_39(w_mux_39.WR_SRAM_NUM),
                .WR_EN_40(w_mux_40.WR_EN),
                .WR_ADDR_40(w_mux_40.WR_ADDR),
                .WR_DATA_40(w_mux_40.WR_DATA),
                .WR_SRAM_NUM_40(w_mux_40.WR_SRAM_NUM),
                .WR_EN_41(w_mux_41.WR_EN),
                .WR_ADDR_41(w_mux_41.WR_ADDR),
                .WR_DATA_41(w_mux_41.WR_DATA),
                .WR_SRAM_NUM_41(w_mux_41.WR_SRAM_NUM),
                .WR_EN_42(w_mux_42.WR_EN),
                .WR_ADDR_42(w_mux_42.WR_ADDR),
                .WR_DATA_42(w_mux_42.WR_DATA),
                .WR_SRAM_NUM_42(w_mux_42.WR_SRAM_NUM),
                .WR_EN_43(w_mux_43.WR_EN),
                .WR_ADDR_43(w_mux_43.WR_ADDR),
                .WR_DATA_43(w_mux_43.WR_DATA),
                .WR_SRAM_NUM_43(w_mux_43.WR_SRAM_NUM),
                .WR_EN_44(w_mux_44.WR_EN),
                .WR_ADDR_44(w_mux_44.WR_ADDR),
                .WR_DATA_44(w_mux_44.WR_DATA),
                .WR_SRAM_NUM_44(w_mux_44.WR_SRAM_NUM),
                .WR_EN_45(w_mux_45.WR_EN),
                .WR_ADDR_45(w_mux_45.WR_ADDR),
                .WR_DATA_45(w_mux_45.WR_DATA),
                .WR_SRAM_NUM_45(w_mux_45.WR_SRAM_NUM),
                .WR_EN_46(w_mux_46.WR_EN),
                .WR_ADDR_46(w_mux_46.WR_ADDR),
                .WR_DATA_46(w_mux_46.WR_DATA),
                .WR_SRAM_NUM_46(w_mux_46.WR_SRAM_NUM),
                .WR_EN_47(w_mux_47.WR_EN),
                .WR_ADDR_47(w_mux_47.WR_ADDR),
                .WR_DATA_47(w_mux_47.WR_DATA),
                .WR_SRAM_NUM_47(w_mux_47.WR_SRAM_NUM),
                .W_DATA(sram_mux_2.W_DATA),
                .W_ADDR(sram_mux_2.W_ADDR),
                .WR(sram_mux_2.WR)
            );
            wr_sram_ctrl#(.WR_SRAM_num(19))
            sram_ctrl_u_3(
                .WR_EN_0(w_mux_0.WR_EN),
                .WR_ADDR_0(w_mux_0.WR_ADDR),
                .WR_DATA_0(w_mux_0.WR_DATA),
                .WR_SRAM_NUM_0(w_mux_0.WR_SRAM_NUM),
                .WR_EN_1(w_mux_1.WR_EN),
                .WR_ADDR_1(w_mux_1.WR_ADDR),
                .WR_DATA_1(w_mux_1.WR_DATA),
                .WR_SRAM_NUM_1(w_mux_1.WR_SRAM_NUM),
                .WR_EN_2(w_mux_2.WR_EN),
                .WR_ADDR_2(w_mux_2.WR_ADDR),
                .WR_DATA_2(w_mux_2.WR_DATA),
                .WR_SRAM_NUM_2(w_mux_2.WR_SRAM_NUM),
                .WR_EN_3(w_mux_3.WR_EN),
                .WR_ADDR_3(w_mux_3.WR_ADDR),
                .WR_DATA_3(w_mux_3.WR_DATA),
                .WR_SRAM_NUM_3(w_mux_3.WR_SRAM_NUM),
                .WR_EN_4(w_mux_4.WR_EN),
                .WR_ADDR_4(w_mux_4.WR_ADDR),
                .WR_DATA_4(w_mux_4.WR_DATA),
                .WR_SRAM_NUM_4(w_mux_4.WR_SRAM_NUM),
                .WR_EN_5(w_mux_5.WR_EN),
                .WR_ADDR_5(w_mux_5.WR_ADDR),
                .WR_DATA_5(w_mux_5.WR_DATA),
                .WR_SRAM_NUM_5(w_mux_5.WR_SRAM_NUM),
                .WR_EN_6(w_mux_6.WR_EN),
                .WR_ADDR_6(w_mux_6.WR_ADDR),
                .WR_DATA_6(w_mux_6.WR_DATA),
                .WR_SRAM_NUM_6(w_mux_6.WR_SRAM_NUM),
                .WR_EN_7(w_mux_7.WR_EN),
                .WR_ADDR_7(w_mux_7.WR_ADDR),
                .WR_DATA_7(w_mux_7.WR_DATA),
                .WR_SRAM_NUM_7(w_mux_7.WR_SRAM_NUM),
                .WR_EN_8(w_mux_8.WR_EN),
                .WR_ADDR_8(w_mux_8.WR_ADDR),
                .WR_DATA_8(w_mux_8.WR_DATA),
                .WR_SRAM_NUM_8(w_mux_8.WR_SRAM_NUM),
                .WR_EN_9(w_mux_9.WR_EN),
                .WR_ADDR_9(w_mux_9.WR_ADDR),
                .WR_DATA_9(w_mux_9.WR_DATA),
                .WR_SRAM_NUM_9(w_mux_9.WR_SRAM_NUM),
                .WR_EN_10(w_mux_10.WR_EN),
                .WR_ADDR_10(w_mux_10.WR_ADDR),
                .WR_DATA_10(w_mux_10.WR_DATA),
                .WR_SRAM_NUM_10(w_mux_10.WR_SRAM_NUM),
                .WR_EN_11(w_mux_11.WR_EN),
                .WR_ADDR_11(w_mux_11.WR_ADDR),
                .WR_DATA_11(w_mux_11.WR_DATA),
                .WR_SRAM_NUM_11(w_mux_11.WR_SRAM_NUM),
                .WR_EN_12(w_mux_12.WR_EN),
                .WR_ADDR_12(w_mux_12.WR_ADDR),
                .WR_DATA_12(w_mux_12.WR_DATA),
                .WR_SRAM_NUM_12(w_mux_12.WR_SRAM_NUM),
                .WR_EN_13(w_mux_13.WR_EN),
                .WR_ADDR_13(w_mux_13.WR_ADDR),
                .WR_DATA_13(w_mux_13.WR_DATA),
                .WR_SRAM_NUM_13(w_mux_13.WR_SRAM_NUM),
                .WR_EN_14(w_mux_14.WR_EN),
                .WR_ADDR_14(w_mux_14.WR_ADDR),
                .WR_DATA_14(w_mux_14.WR_DATA),
                .WR_SRAM_NUM_14(w_mux_14.WR_SRAM_NUM),
                .WR_EN_15(w_mux_15.WR_EN),
                .WR_ADDR_15(w_mux_15.WR_ADDR),
                .WR_DATA_15(w_mux_15.WR_DATA),
                .WR_SRAM_NUM_15(w_mux_15.WR_SRAM_NUM),
                .WR_EN_16(w_mux_16.WR_EN),
                .WR_ADDR_16(w_mux_16.WR_ADDR),
                .WR_DATA_16(w_mux_16.WR_DATA),
                .WR_SRAM_NUM_16(w_mux_16.WR_SRAM_NUM),
                .WR_EN_17(w_mux_17.WR_EN),
                .WR_ADDR_17(w_mux_17.WR_ADDR),
                .WR_DATA_17(w_mux_17.WR_DATA),
                .WR_SRAM_NUM_17(w_mux_17.WR_SRAM_NUM),
                .WR_EN_18(w_mux_18.WR_EN),
                .WR_ADDR_18(w_mux_18.WR_ADDR),
                .WR_DATA_18(w_mux_18.WR_DATA),
                .WR_SRAM_NUM_18(w_mux_18.WR_SRAM_NUM),
                .WR_EN_19(w_mux_19.WR_EN),
                .WR_ADDR_19(w_mux_19.WR_ADDR),
                .WR_DATA_19(w_mux_19.WR_DATA),
                .WR_SRAM_NUM_19(w_mux_19.WR_SRAM_NUM),
                .WR_EN_20(w_mux_20.WR_EN),
                .WR_ADDR_20(w_mux_20.WR_ADDR),
                .WR_DATA_20(w_mux_20.WR_DATA),
                .WR_SRAM_NUM_20(w_mux_20.WR_SRAM_NUM),
                .WR_EN_21(w_mux_21.WR_EN),
                .WR_ADDR_21(w_mux_21.WR_ADDR),
                .WR_DATA_21(w_mux_21.WR_DATA),
                .WR_SRAM_NUM_21(w_mux_21.WR_SRAM_NUM),
                .WR_EN_22(w_mux_22.WR_EN),
                .WR_ADDR_22(w_mux_22.WR_ADDR),
                .WR_DATA_22(w_mux_22.WR_DATA),
                .WR_SRAM_NUM_22(w_mux_22.WR_SRAM_NUM),
                .WR_EN_23(w_mux_23.WR_EN),
                .WR_ADDR_23(w_mux_23.WR_ADDR),
                .WR_DATA_23(w_mux_23.WR_DATA),
                .WR_SRAM_NUM_23(w_mux_23.WR_SRAM_NUM),
                .WR_EN_24(w_mux_24.WR_EN),
                .WR_ADDR_24(w_mux_24.WR_ADDR),
                .WR_DATA_24(w_mux_24.WR_DATA),
                .WR_SRAM_NUM_24(w_mux_24.WR_SRAM_NUM),
                .WR_EN_25(w_mux_25.WR_EN),
                .WR_ADDR_25(w_mux_25.WR_ADDR),
                .WR_DATA_25(w_mux_25.WR_DATA),
                .WR_SRAM_NUM_25(w_mux_25.WR_SRAM_NUM),
                .WR_EN_26(w_mux_26.WR_EN),
                .WR_ADDR_26(w_mux_26.WR_ADDR),
                .WR_DATA_26(w_mux_26.WR_DATA),
                .WR_SRAM_NUM_26(w_mux_26.WR_SRAM_NUM),
                .WR_EN_27(w_mux_27.WR_EN),
                .WR_ADDR_27(w_mux_27.WR_ADDR),
                .WR_DATA_27(w_mux_27.WR_DATA),
                .WR_SRAM_NUM_27(w_mux_27.WR_SRAM_NUM),
                .WR_EN_28(w_mux_28.WR_EN),
                .WR_ADDR_28(w_mux_28.WR_ADDR),
                .WR_DATA_28(w_mux_28.WR_DATA),
                .WR_SRAM_NUM_28(w_mux_28.WR_SRAM_NUM),
                .WR_EN_29(w_mux_29.WR_EN),
                .WR_ADDR_29(w_mux_29.WR_ADDR),
                .WR_DATA_29(w_mux_29.WR_DATA),
                .WR_SRAM_NUM_29(w_mux_29.WR_SRAM_NUM),
                .WR_EN_30(w_mux_30.WR_EN),
                .WR_ADDR_30(w_mux_30.WR_ADDR),
                .WR_DATA_30(w_mux_30.WR_DATA),
                .WR_SRAM_NUM_30(w_mux_30.WR_SRAM_NUM),
                .WR_EN_31(w_mux_31.WR_EN),
                .WR_ADDR_31(w_mux_31.WR_ADDR),
                .WR_DATA_31(w_mux_31.WR_DATA),
                .WR_SRAM_NUM_31(w_mux_31.WR_SRAM_NUM),
                .WR_EN_32(w_mux_32.WR_EN),
                .WR_ADDR_32(w_mux_32.WR_ADDR),
                .WR_DATA_32(w_mux_32.WR_DATA),
                .WR_SRAM_NUM_32(w_mux_32.WR_SRAM_NUM),
                .WR_EN_33(w_mux_33.WR_EN),
                .WR_ADDR_33(w_mux_33.WR_ADDR),
                .WR_DATA_33(w_mux_33.WR_DATA),
                .WR_SRAM_NUM_33(w_mux_33.WR_SRAM_NUM),
                .WR_EN_34(w_mux_34.WR_EN),
                .WR_ADDR_34(w_mux_34.WR_ADDR),
                .WR_DATA_34(w_mux_34.WR_DATA),
                .WR_SRAM_NUM_34(w_mux_34.WR_SRAM_NUM),
                .WR_EN_35(w_mux_35.WR_EN),
                .WR_ADDR_35(w_mux_35.WR_ADDR),
                .WR_DATA_35(w_mux_35.WR_DATA),
                .WR_SRAM_NUM_35(w_mux_35.WR_SRAM_NUM),
                .WR_EN_36(w_mux_36.WR_EN),
                .WR_ADDR_36(w_mux_36.WR_ADDR),
                .WR_DATA_36(w_mux_36.WR_DATA),
                .WR_SRAM_NUM_36(w_mux_36.WR_SRAM_NUM),
                .WR_EN_37(w_mux_37.WR_EN),
                .WR_ADDR_37(w_mux_37.WR_ADDR),
                .WR_DATA_37(w_mux_37.WR_DATA),
                .WR_SRAM_NUM_37(w_mux_37.WR_SRAM_NUM),
                .WR_EN_38(w_mux_38.WR_EN),
                .WR_ADDR_38(w_mux_38.WR_ADDR),
                .WR_DATA_38(w_mux_38.WR_DATA),
                .WR_SRAM_NUM_38(w_mux_38.WR_SRAM_NUM),
                .WR_EN_39(w_mux_39.WR_EN),
                .WR_ADDR_39(w_mux_39.WR_ADDR),
                .WR_DATA_39(w_mux_39.WR_DATA),
                .WR_SRAM_NUM_39(w_mux_39.WR_SRAM_NUM),
                .WR_EN_40(w_mux_40.WR_EN),
                .WR_ADDR_40(w_mux_40.WR_ADDR),
                .WR_DATA_40(w_mux_40.WR_DATA),
                .WR_SRAM_NUM_40(w_mux_40.WR_SRAM_NUM),
                .WR_EN_41(w_mux_41.WR_EN),
                .WR_ADDR_41(w_mux_41.WR_ADDR),
                .WR_DATA_41(w_mux_41.WR_DATA),
                .WR_SRAM_NUM_41(w_mux_41.WR_SRAM_NUM),
                .WR_EN_42(w_mux_42.WR_EN),
                .WR_ADDR_42(w_mux_42.WR_ADDR),
                .WR_DATA_42(w_mux_42.WR_DATA),
                .WR_SRAM_NUM_42(w_mux_42.WR_SRAM_NUM),
                .WR_EN_43(w_mux_43.WR_EN),
                .WR_ADDR_43(w_mux_43.WR_ADDR),
                .WR_DATA_43(w_mux_43.WR_DATA),
                .WR_SRAM_NUM_43(w_mux_43.WR_SRAM_NUM),
                .WR_EN_44(w_mux_44.WR_EN),
                .WR_ADDR_44(w_mux_44.WR_ADDR),
                .WR_DATA_44(w_mux_44.WR_DATA),
                .WR_SRAM_NUM_44(w_mux_44.WR_SRAM_NUM),
                .WR_EN_45(w_mux_45.WR_EN),
                .WR_ADDR_45(w_mux_45.WR_ADDR),
                .WR_DATA_45(w_mux_45.WR_DATA),
                .WR_SRAM_NUM_45(w_mux_45.WR_SRAM_NUM),
                .WR_EN_46(w_mux_46.WR_EN),
                .WR_ADDR_46(w_mux_46.WR_ADDR),
                .WR_DATA_46(w_mux_46.WR_DATA),
                .WR_SRAM_NUM_46(w_mux_46.WR_SRAM_NUM),
                .WR_EN_47(w_mux_47.WR_EN),
                .WR_ADDR_47(w_mux_47.WR_ADDR),
                .WR_DATA_47(w_mux_47.WR_DATA),
                .WR_SRAM_NUM_47(w_mux_47.WR_SRAM_NUM),
                .W_DATA(sram_mux_3.W_DATA),
                .W_ADDR(sram_mux_3.W_ADDR),
                .WR(sram_mux_3.WR)
            );
            wr_sram_ctrl#(.WR_SRAM_num(20))
            sram_ctrl_u_4(
                .WR_EN_0(w_mux_0.WR_EN),
                .WR_ADDR_0(w_mux_0.WR_ADDR),
                .WR_DATA_0(w_mux_0.WR_DATA),
                .WR_SRAM_NUM_0(w_mux_0.WR_SRAM_NUM),
                .WR_EN_1(w_mux_1.WR_EN),
                .WR_ADDR_1(w_mux_1.WR_ADDR),
                .WR_DATA_1(w_mux_1.WR_DATA),
                .WR_SRAM_NUM_1(w_mux_1.WR_SRAM_NUM),
                .WR_EN_2(w_mux_2.WR_EN),
                .WR_ADDR_2(w_mux_2.WR_ADDR),
                .WR_DATA_2(w_mux_2.WR_DATA),
                .WR_SRAM_NUM_2(w_mux_2.WR_SRAM_NUM),
                .WR_EN_3(w_mux_3.WR_EN),
                .WR_ADDR_3(w_mux_3.WR_ADDR),
                .WR_DATA_3(w_mux_3.WR_DATA),
                .WR_SRAM_NUM_3(w_mux_3.WR_SRAM_NUM),
                .WR_EN_4(w_mux_4.WR_EN),
                .WR_ADDR_4(w_mux_4.WR_ADDR),
                .WR_DATA_4(w_mux_4.WR_DATA),
                .WR_SRAM_NUM_4(w_mux_4.WR_SRAM_NUM),
                .WR_EN_5(w_mux_5.WR_EN),
                .WR_ADDR_5(w_mux_5.WR_ADDR),
                .WR_DATA_5(w_mux_5.WR_DATA),
                .WR_SRAM_NUM_5(w_mux_5.WR_SRAM_NUM),
                .WR_EN_6(w_mux_6.WR_EN),
                .WR_ADDR_6(w_mux_6.WR_ADDR),
                .WR_DATA_6(w_mux_6.WR_DATA),
                .WR_SRAM_NUM_6(w_mux_6.WR_SRAM_NUM),
                .WR_EN_7(w_mux_7.WR_EN),
                .WR_ADDR_7(w_mux_7.WR_ADDR),
                .WR_DATA_7(w_mux_7.WR_DATA),
                .WR_SRAM_NUM_7(w_mux_7.WR_SRAM_NUM),
                .WR_EN_8(w_mux_8.WR_EN),
                .WR_ADDR_8(w_mux_8.WR_ADDR),
                .WR_DATA_8(w_mux_8.WR_DATA),
                .WR_SRAM_NUM_8(w_mux_8.WR_SRAM_NUM),
                .WR_EN_9(w_mux_9.WR_EN),
                .WR_ADDR_9(w_mux_9.WR_ADDR),
                .WR_DATA_9(w_mux_9.WR_DATA),
                .WR_SRAM_NUM_9(w_mux_9.WR_SRAM_NUM),
                .WR_EN_10(w_mux_10.WR_EN),
                .WR_ADDR_10(w_mux_10.WR_ADDR),
                .WR_DATA_10(w_mux_10.WR_DATA),
                .WR_SRAM_NUM_10(w_mux_10.WR_SRAM_NUM),
                .WR_EN_11(w_mux_11.WR_EN),
                .WR_ADDR_11(w_mux_11.WR_ADDR),
                .WR_DATA_11(w_mux_11.WR_DATA),
                .WR_SRAM_NUM_11(w_mux_11.WR_SRAM_NUM),
                .WR_EN_12(w_mux_12.WR_EN),
                .WR_ADDR_12(w_mux_12.WR_ADDR),
                .WR_DATA_12(w_mux_12.WR_DATA),
                .WR_SRAM_NUM_12(w_mux_12.WR_SRAM_NUM),
                .WR_EN_13(w_mux_13.WR_EN),
                .WR_ADDR_13(w_mux_13.WR_ADDR),
                .WR_DATA_13(w_mux_13.WR_DATA),
                .WR_SRAM_NUM_13(w_mux_13.WR_SRAM_NUM),
                .WR_EN_14(w_mux_14.WR_EN),
                .WR_ADDR_14(w_mux_14.WR_ADDR),
                .WR_DATA_14(w_mux_14.WR_DATA),
                .WR_SRAM_NUM_14(w_mux_14.WR_SRAM_NUM),
                .WR_EN_15(w_mux_15.WR_EN),
                .WR_ADDR_15(w_mux_15.WR_ADDR),
                .WR_DATA_15(w_mux_15.WR_DATA),
                .WR_SRAM_NUM_15(w_mux_15.WR_SRAM_NUM),
                .WR_EN_16(w_mux_16.WR_EN),
                .WR_ADDR_16(w_mux_16.WR_ADDR),
                .WR_DATA_16(w_mux_16.WR_DATA),
                .WR_SRAM_NUM_16(w_mux_16.WR_SRAM_NUM),
                .WR_EN_17(w_mux_17.WR_EN),
                .WR_ADDR_17(w_mux_17.WR_ADDR),
                .WR_DATA_17(w_mux_17.WR_DATA),
                .WR_SRAM_NUM_17(w_mux_17.WR_SRAM_NUM),
                .WR_EN_18(w_mux_18.WR_EN),
                .WR_ADDR_18(w_mux_18.WR_ADDR),
                .WR_DATA_18(w_mux_18.WR_DATA),
                .WR_SRAM_NUM_18(w_mux_18.WR_SRAM_NUM),
                .WR_EN_19(w_mux_19.WR_EN),
                .WR_ADDR_19(w_mux_19.WR_ADDR),
                .WR_DATA_19(w_mux_19.WR_DATA),
                .WR_SRAM_NUM_19(w_mux_19.WR_SRAM_NUM),
                .WR_EN_20(w_mux_20.WR_EN),
                .WR_ADDR_20(w_mux_20.WR_ADDR),
                .WR_DATA_20(w_mux_20.WR_DATA),
                .WR_SRAM_NUM_20(w_mux_20.WR_SRAM_NUM),
                .WR_EN_21(w_mux_21.WR_EN),
                .WR_ADDR_21(w_mux_21.WR_ADDR),
                .WR_DATA_21(w_mux_21.WR_DATA),
                .WR_SRAM_NUM_21(w_mux_21.WR_SRAM_NUM),
                .WR_EN_22(w_mux_22.WR_EN),
                .WR_ADDR_22(w_mux_22.WR_ADDR),
                .WR_DATA_22(w_mux_22.WR_DATA),
                .WR_SRAM_NUM_22(w_mux_22.WR_SRAM_NUM),
                .WR_EN_23(w_mux_23.WR_EN),
                .WR_ADDR_23(w_mux_23.WR_ADDR),
                .WR_DATA_23(w_mux_23.WR_DATA),
                .WR_SRAM_NUM_23(w_mux_23.WR_SRAM_NUM),
                .WR_EN_24(w_mux_24.WR_EN),
                .WR_ADDR_24(w_mux_24.WR_ADDR),
                .WR_DATA_24(w_mux_24.WR_DATA),
                .WR_SRAM_NUM_24(w_mux_24.WR_SRAM_NUM),
                .WR_EN_25(w_mux_25.WR_EN),
                .WR_ADDR_25(w_mux_25.WR_ADDR),
                .WR_DATA_25(w_mux_25.WR_DATA),
                .WR_SRAM_NUM_25(w_mux_25.WR_SRAM_NUM),
                .WR_EN_26(w_mux_26.WR_EN),
                .WR_ADDR_26(w_mux_26.WR_ADDR),
                .WR_DATA_26(w_mux_26.WR_DATA),
                .WR_SRAM_NUM_26(w_mux_26.WR_SRAM_NUM),
                .WR_EN_27(w_mux_27.WR_EN),
                .WR_ADDR_27(w_mux_27.WR_ADDR),
                .WR_DATA_27(w_mux_27.WR_DATA),
                .WR_SRAM_NUM_27(w_mux_27.WR_SRAM_NUM),
                .WR_EN_28(w_mux_28.WR_EN),
                .WR_ADDR_28(w_mux_28.WR_ADDR),
                .WR_DATA_28(w_mux_28.WR_DATA),
                .WR_SRAM_NUM_28(w_mux_28.WR_SRAM_NUM),
                .WR_EN_29(w_mux_29.WR_EN),
                .WR_ADDR_29(w_mux_29.WR_ADDR),
                .WR_DATA_29(w_mux_29.WR_DATA),
                .WR_SRAM_NUM_29(w_mux_29.WR_SRAM_NUM),
                .WR_EN_30(w_mux_30.WR_EN),
                .WR_ADDR_30(w_mux_30.WR_ADDR),
                .WR_DATA_30(w_mux_30.WR_DATA),
                .WR_SRAM_NUM_30(w_mux_30.WR_SRAM_NUM),
                .WR_EN_31(w_mux_31.WR_EN),
                .WR_ADDR_31(w_mux_31.WR_ADDR),
                .WR_DATA_31(w_mux_31.WR_DATA),
                .WR_SRAM_NUM_31(w_mux_31.WR_SRAM_NUM),
                .WR_EN_32(w_mux_32.WR_EN),
                .WR_ADDR_32(w_mux_32.WR_ADDR),
                .WR_DATA_32(w_mux_32.WR_DATA),
                .WR_SRAM_NUM_32(w_mux_32.WR_SRAM_NUM),
                .WR_EN_33(w_mux_33.WR_EN),
                .WR_ADDR_33(w_mux_33.WR_ADDR),
                .WR_DATA_33(w_mux_33.WR_DATA),
                .WR_SRAM_NUM_33(w_mux_33.WR_SRAM_NUM),
                .WR_EN_34(w_mux_34.WR_EN),
                .WR_ADDR_34(w_mux_34.WR_ADDR),
                .WR_DATA_34(w_mux_34.WR_DATA),
                .WR_SRAM_NUM_34(w_mux_34.WR_SRAM_NUM),
                .WR_EN_35(w_mux_35.WR_EN),
                .WR_ADDR_35(w_mux_35.WR_ADDR),
                .WR_DATA_35(w_mux_35.WR_DATA),
                .WR_SRAM_NUM_35(w_mux_35.WR_SRAM_NUM),
                .WR_EN_36(w_mux_36.WR_EN),
                .WR_ADDR_36(w_mux_36.WR_ADDR),
                .WR_DATA_36(w_mux_36.WR_DATA),
                .WR_SRAM_NUM_36(w_mux_36.WR_SRAM_NUM),
                .WR_EN_37(w_mux_37.WR_EN),
                .WR_ADDR_37(w_mux_37.WR_ADDR),
                .WR_DATA_37(w_mux_37.WR_DATA),
                .WR_SRAM_NUM_37(w_mux_37.WR_SRAM_NUM),
                .WR_EN_38(w_mux_38.WR_EN),
                .WR_ADDR_38(w_mux_38.WR_ADDR),
                .WR_DATA_38(w_mux_38.WR_DATA),
                .WR_SRAM_NUM_38(w_mux_38.WR_SRAM_NUM),
                .WR_EN_39(w_mux_39.WR_EN),
                .WR_ADDR_39(w_mux_39.WR_ADDR),
                .WR_DATA_39(w_mux_39.WR_DATA),
                .WR_SRAM_NUM_39(w_mux_39.WR_SRAM_NUM),
                .WR_EN_40(w_mux_40.WR_EN),
                .WR_ADDR_40(w_mux_40.WR_ADDR),
                .WR_DATA_40(w_mux_40.WR_DATA),
                .WR_SRAM_NUM_40(w_mux_40.WR_SRAM_NUM),
                .WR_EN_41(w_mux_41.WR_EN),
                .WR_ADDR_41(w_mux_41.WR_ADDR),
                .WR_DATA_41(w_mux_41.WR_DATA),
                .WR_SRAM_NUM_41(w_mux_41.WR_SRAM_NUM),
                .WR_EN_42(w_mux_42.WR_EN),
                .WR_ADDR_42(w_mux_42.WR_ADDR),
                .WR_DATA_42(w_mux_42.WR_DATA),
                .WR_SRAM_NUM_42(w_mux_42.WR_SRAM_NUM),
                .WR_EN_43(w_mux_43.WR_EN),
                .WR_ADDR_43(w_mux_43.WR_ADDR),
                .WR_DATA_43(w_mux_43.WR_DATA),
                .WR_SRAM_NUM_43(w_mux_43.WR_SRAM_NUM),
                .WR_EN_44(w_mux_44.WR_EN),
                .WR_ADDR_44(w_mux_44.WR_ADDR),
                .WR_DATA_44(w_mux_44.WR_DATA),
                .WR_SRAM_NUM_44(w_mux_44.WR_SRAM_NUM),
                .WR_EN_45(w_mux_45.WR_EN),
                .WR_ADDR_45(w_mux_45.WR_ADDR),
                .WR_DATA_45(w_mux_45.WR_DATA),
                .WR_SRAM_NUM_45(w_mux_45.WR_SRAM_NUM),
                .WR_EN_46(w_mux_46.WR_EN),
                .WR_ADDR_46(w_mux_46.WR_ADDR),
                .WR_DATA_46(w_mux_46.WR_DATA),
                .WR_SRAM_NUM_46(w_mux_46.WR_SRAM_NUM),
                .WR_EN_47(w_mux_47.WR_EN),
                .WR_ADDR_47(w_mux_47.WR_ADDR),
                .WR_DATA_47(w_mux_47.WR_DATA),
                .WR_SRAM_NUM_47(w_mux_47.WR_SRAM_NUM),
                .W_DATA(sram_mux_4.W_DATA),
                .W_ADDR(sram_mux_4.W_ADDR),
                .WR(sram_mux_4.WR)
            );
            wr_sram_ctrl#(.WR_SRAM_num(21))
            sram_ctrl_u_5(
                .WR_EN_0(w_mux_0.WR_EN),
                .WR_ADDR_0(w_mux_0.WR_ADDR),
                .WR_DATA_0(w_mux_0.WR_DATA),
                .WR_SRAM_NUM_0(w_mux_0.WR_SRAM_NUM),
                .WR_EN_1(w_mux_1.WR_EN),
                .WR_ADDR_1(w_mux_1.WR_ADDR),
                .WR_DATA_1(w_mux_1.WR_DATA),
                .WR_SRAM_NUM_1(w_mux_1.WR_SRAM_NUM),
                .WR_EN_2(w_mux_2.WR_EN),
                .WR_ADDR_2(w_mux_2.WR_ADDR),
                .WR_DATA_2(w_mux_2.WR_DATA),
                .WR_SRAM_NUM_2(w_mux_2.WR_SRAM_NUM),
                .WR_EN_3(w_mux_3.WR_EN),
                .WR_ADDR_3(w_mux_3.WR_ADDR),
                .WR_DATA_3(w_mux_3.WR_DATA),
                .WR_SRAM_NUM_3(w_mux_3.WR_SRAM_NUM),
                .WR_EN_4(w_mux_4.WR_EN),
                .WR_ADDR_4(w_mux_4.WR_ADDR),
                .WR_DATA_4(w_mux_4.WR_DATA),
                .WR_SRAM_NUM_4(w_mux_4.WR_SRAM_NUM),
                .WR_EN_5(w_mux_5.WR_EN),
                .WR_ADDR_5(w_mux_5.WR_ADDR),
                .WR_DATA_5(w_mux_5.WR_DATA),
                .WR_SRAM_NUM_5(w_mux_5.WR_SRAM_NUM),
                .WR_EN_6(w_mux_6.WR_EN),
                .WR_ADDR_6(w_mux_6.WR_ADDR),
                .WR_DATA_6(w_mux_6.WR_DATA),
                .WR_SRAM_NUM_6(w_mux_6.WR_SRAM_NUM),
                .WR_EN_7(w_mux_7.WR_EN),
                .WR_ADDR_7(w_mux_7.WR_ADDR),
                .WR_DATA_7(w_mux_7.WR_DATA),
                .WR_SRAM_NUM_7(w_mux_7.WR_SRAM_NUM),
                .WR_EN_8(w_mux_8.WR_EN),
                .WR_ADDR_8(w_mux_8.WR_ADDR),
                .WR_DATA_8(w_mux_8.WR_DATA),
                .WR_SRAM_NUM_8(w_mux_8.WR_SRAM_NUM),
                .WR_EN_9(w_mux_9.WR_EN),
                .WR_ADDR_9(w_mux_9.WR_ADDR),
                .WR_DATA_9(w_mux_9.WR_DATA),
                .WR_SRAM_NUM_9(w_mux_9.WR_SRAM_NUM),
                .WR_EN_10(w_mux_10.WR_EN),
                .WR_ADDR_10(w_mux_10.WR_ADDR),
                .WR_DATA_10(w_mux_10.WR_DATA),
                .WR_SRAM_NUM_10(w_mux_10.WR_SRAM_NUM),
                .WR_EN_11(w_mux_11.WR_EN),
                .WR_ADDR_11(w_mux_11.WR_ADDR),
                .WR_DATA_11(w_mux_11.WR_DATA),
                .WR_SRAM_NUM_11(w_mux_11.WR_SRAM_NUM),
                .WR_EN_12(w_mux_12.WR_EN),
                .WR_ADDR_12(w_mux_12.WR_ADDR),
                .WR_DATA_12(w_mux_12.WR_DATA),
                .WR_SRAM_NUM_12(w_mux_12.WR_SRAM_NUM),
                .WR_EN_13(w_mux_13.WR_EN),
                .WR_ADDR_13(w_mux_13.WR_ADDR),
                .WR_DATA_13(w_mux_13.WR_DATA),
                .WR_SRAM_NUM_13(w_mux_13.WR_SRAM_NUM),
                .WR_EN_14(w_mux_14.WR_EN),
                .WR_ADDR_14(w_mux_14.WR_ADDR),
                .WR_DATA_14(w_mux_14.WR_DATA),
                .WR_SRAM_NUM_14(w_mux_14.WR_SRAM_NUM),
                .WR_EN_15(w_mux_15.WR_EN),
                .WR_ADDR_15(w_mux_15.WR_ADDR),
                .WR_DATA_15(w_mux_15.WR_DATA),
                .WR_SRAM_NUM_15(w_mux_15.WR_SRAM_NUM),
                .WR_EN_16(w_mux_16.WR_EN),
                .WR_ADDR_16(w_mux_16.WR_ADDR),
                .WR_DATA_16(w_mux_16.WR_DATA),
                .WR_SRAM_NUM_16(w_mux_16.WR_SRAM_NUM),
                .WR_EN_17(w_mux_17.WR_EN),
                .WR_ADDR_17(w_mux_17.WR_ADDR),
                .WR_DATA_17(w_mux_17.WR_DATA),
                .WR_SRAM_NUM_17(w_mux_17.WR_SRAM_NUM),
                .WR_EN_18(w_mux_18.WR_EN),
                .WR_ADDR_18(w_mux_18.WR_ADDR),
                .WR_DATA_18(w_mux_18.WR_DATA),
                .WR_SRAM_NUM_18(w_mux_18.WR_SRAM_NUM),
                .WR_EN_19(w_mux_19.WR_EN),
                .WR_ADDR_19(w_mux_19.WR_ADDR),
                .WR_DATA_19(w_mux_19.WR_DATA),
                .WR_SRAM_NUM_19(w_mux_19.WR_SRAM_NUM),
                .WR_EN_20(w_mux_20.WR_EN),
                .WR_ADDR_20(w_mux_20.WR_ADDR),
                .WR_DATA_20(w_mux_20.WR_DATA),
                .WR_SRAM_NUM_20(w_mux_20.WR_SRAM_NUM),
                .WR_EN_21(w_mux_21.WR_EN),
                .WR_ADDR_21(w_mux_21.WR_ADDR),
                .WR_DATA_21(w_mux_21.WR_DATA),
                .WR_SRAM_NUM_21(w_mux_21.WR_SRAM_NUM),
                .WR_EN_22(w_mux_22.WR_EN),
                .WR_ADDR_22(w_mux_22.WR_ADDR),
                .WR_DATA_22(w_mux_22.WR_DATA),
                .WR_SRAM_NUM_22(w_mux_22.WR_SRAM_NUM),
                .WR_EN_23(w_mux_23.WR_EN),
                .WR_ADDR_23(w_mux_23.WR_ADDR),
                .WR_DATA_23(w_mux_23.WR_DATA),
                .WR_SRAM_NUM_23(w_mux_23.WR_SRAM_NUM),
                .WR_EN_24(w_mux_24.WR_EN),
                .WR_ADDR_24(w_mux_24.WR_ADDR),
                .WR_DATA_24(w_mux_24.WR_DATA),
                .WR_SRAM_NUM_24(w_mux_24.WR_SRAM_NUM),
                .WR_EN_25(w_mux_25.WR_EN),
                .WR_ADDR_25(w_mux_25.WR_ADDR),
                .WR_DATA_25(w_mux_25.WR_DATA),
                .WR_SRAM_NUM_25(w_mux_25.WR_SRAM_NUM),
                .WR_EN_26(w_mux_26.WR_EN),
                .WR_ADDR_26(w_mux_26.WR_ADDR),
                .WR_DATA_26(w_mux_26.WR_DATA),
                .WR_SRAM_NUM_26(w_mux_26.WR_SRAM_NUM),
                .WR_EN_27(w_mux_27.WR_EN),
                .WR_ADDR_27(w_mux_27.WR_ADDR),
                .WR_DATA_27(w_mux_27.WR_DATA),
                .WR_SRAM_NUM_27(w_mux_27.WR_SRAM_NUM),
                .WR_EN_28(w_mux_28.WR_EN),
                .WR_ADDR_28(w_mux_28.WR_ADDR),
                .WR_DATA_28(w_mux_28.WR_DATA),
                .WR_SRAM_NUM_28(w_mux_28.WR_SRAM_NUM),
                .WR_EN_29(w_mux_29.WR_EN),
                .WR_ADDR_29(w_mux_29.WR_ADDR),
                .WR_DATA_29(w_mux_29.WR_DATA),
                .WR_SRAM_NUM_29(w_mux_29.WR_SRAM_NUM),
                .WR_EN_30(w_mux_30.WR_EN),
                .WR_ADDR_30(w_mux_30.WR_ADDR),
                .WR_DATA_30(w_mux_30.WR_DATA),
                .WR_SRAM_NUM_30(w_mux_30.WR_SRAM_NUM),
                .WR_EN_31(w_mux_31.WR_EN),
                .WR_ADDR_31(w_mux_31.WR_ADDR),
                .WR_DATA_31(w_mux_31.WR_DATA),
                .WR_SRAM_NUM_31(w_mux_31.WR_SRAM_NUM),
                .WR_EN_32(w_mux_32.WR_EN),
                .WR_ADDR_32(w_mux_32.WR_ADDR),
                .WR_DATA_32(w_mux_32.WR_DATA),
                .WR_SRAM_NUM_32(w_mux_32.WR_SRAM_NUM),
                .WR_EN_33(w_mux_33.WR_EN),
                .WR_ADDR_33(w_mux_33.WR_ADDR),
                .WR_DATA_33(w_mux_33.WR_DATA),
                .WR_SRAM_NUM_33(w_mux_33.WR_SRAM_NUM),
                .WR_EN_34(w_mux_34.WR_EN),
                .WR_ADDR_34(w_mux_34.WR_ADDR),
                .WR_DATA_34(w_mux_34.WR_DATA),
                .WR_SRAM_NUM_34(w_mux_34.WR_SRAM_NUM),
                .WR_EN_35(w_mux_35.WR_EN),
                .WR_ADDR_35(w_mux_35.WR_ADDR),
                .WR_DATA_35(w_mux_35.WR_DATA),
                .WR_SRAM_NUM_35(w_mux_35.WR_SRAM_NUM),
                .WR_EN_36(w_mux_36.WR_EN),
                .WR_ADDR_36(w_mux_36.WR_ADDR),
                .WR_DATA_36(w_mux_36.WR_DATA),
                .WR_SRAM_NUM_36(w_mux_36.WR_SRAM_NUM),
                .WR_EN_37(w_mux_37.WR_EN),
                .WR_ADDR_37(w_mux_37.WR_ADDR),
                .WR_DATA_37(w_mux_37.WR_DATA),
                .WR_SRAM_NUM_37(w_mux_37.WR_SRAM_NUM),
                .WR_EN_38(w_mux_38.WR_EN),
                .WR_ADDR_38(w_mux_38.WR_ADDR),
                .WR_DATA_38(w_mux_38.WR_DATA),
                .WR_SRAM_NUM_38(w_mux_38.WR_SRAM_NUM),
                .WR_EN_39(w_mux_39.WR_EN),
                .WR_ADDR_39(w_mux_39.WR_ADDR),
                .WR_DATA_39(w_mux_39.WR_DATA),
                .WR_SRAM_NUM_39(w_mux_39.WR_SRAM_NUM),
                .WR_EN_40(w_mux_40.WR_EN),
                .WR_ADDR_40(w_mux_40.WR_ADDR),
                .WR_DATA_40(w_mux_40.WR_DATA),
                .WR_SRAM_NUM_40(w_mux_40.WR_SRAM_NUM),
                .WR_EN_41(w_mux_41.WR_EN),
                .WR_ADDR_41(w_mux_41.WR_ADDR),
                .WR_DATA_41(w_mux_41.WR_DATA),
                .WR_SRAM_NUM_41(w_mux_41.WR_SRAM_NUM),
                .WR_EN_42(w_mux_42.WR_EN),
                .WR_ADDR_42(w_mux_42.WR_ADDR),
                .WR_DATA_42(w_mux_42.WR_DATA),
                .WR_SRAM_NUM_42(w_mux_42.WR_SRAM_NUM),
                .WR_EN_43(w_mux_43.WR_EN),
                .WR_ADDR_43(w_mux_43.WR_ADDR),
                .WR_DATA_43(w_mux_43.WR_DATA),
                .WR_SRAM_NUM_43(w_mux_43.WR_SRAM_NUM),
                .WR_EN_44(w_mux_44.WR_EN),
                .WR_ADDR_44(w_mux_44.WR_ADDR),
                .WR_DATA_44(w_mux_44.WR_DATA),
                .WR_SRAM_NUM_44(w_mux_44.WR_SRAM_NUM),
                .WR_EN_45(w_mux_45.WR_EN),
                .WR_ADDR_45(w_mux_45.WR_ADDR),
                .WR_DATA_45(w_mux_45.WR_DATA),
                .WR_SRAM_NUM_45(w_mux_45.WR_SRAM_NUM),
                .WR_EN_46(w_mux_46.WR_EN),
                .WR_ADDR_46(w_mux_46.WR_ADDR),
                .WR_DATA_46(w_mux_46.WR_DATA),
                .WR_SRAM_NUM_46(w_mux_46.WR_SRAM_NUM),
                .WR_EN_47(w_mux_47.WR_EN),
                .WR_ADDR_47(w_mux_47.WR_ADDR),
                .WR_DATA_47(w_mux_47.WR_DATA),
                .WR_SRAM_NUM_47(w_mux_47.WR_SRAM_NUM),
                .W_DATA(sram_mux_5.W_DATA),
                .W_ADDR(sram_mux_5.W_ADDR),
                .WR(sram_mux_5.WR)
            );
            wr_sram_ctrl#(.WR_SRAM_num(22))
            sram_ctrl_u_6(
                .WR_EN_0(w_mux_0.WR_EN),
                .WR_ADDR_0(w_mux_0.WR_ADDR),
                .WR_DATA_0(w_mux_0.WR_DATA),
                .WR_SRAM_NUM_0(w_mux_0.WR_SRAM_NUM),
                .WR_EN_1(w_mux_1.WR_EN),
                .WR_ADDR_1(w_mux_1.WR_ADDR),
                .WR_DATA_1(w_mux_1.WR_DATA),
                .WR_SRAM_NUM_1(w_mux_1.WR_SRAM_NUM),
                .WR_EN_2(w_mux_2.WR_EN),
                .WR_ADDR_2(w_mux_2.WR_ADDR),
                .WR_DATA_2(w_mux_2.WR_DATA),
                .WR_SRAM_NUM_2(w_mux_2.WR_SRAM_NUM),
                .WR_EN_3(w_mux_3.WR_EN),
                .WR_ADDR_3(w_mux_3.WR_ADDR),
                .WR_DATA_3(w_mux_3.WR_DATA),
                .WR_SRAM_NUM_3(w_mux_3.WR_SRAM_NUM),
                .WR_EN_4(w_mux_4.WR_EN),
                .WR_ADDR_4(w_mux_4.WR_ADDR),
                .WR_DATA_4(w_mux_4.WR_DATA),
                .WR_SRAM_NUM_4(w_mux_4.WR_SRAM_NUM),
                .WR_EN_5(w_mux_5.WR_EN),
                .WR_ADDR_5(w_mux_5.WR_ADDR),
                .WR_DATA_5(w_mux_5.WR_DATA),
                .WR_SRAM_NUM_5(w_mux_5.WR_SRAM_NUM),
                .WR_EN_6(w_mux_6.WR_EN),
                .WR_ADDR_6(w_mux_6.WR_ADDR),
                .WR_DATA_6(w_mux_6.WR_DATA),
                .WR_SRAM_NUM_6(w_mux_6.WR_SRAM_NUM),
                .WR_EN_7(w_mux_7.WR_EN),
                .WR_ADDR_7(w_mux_7.WR_ADDR),
                .WR_DATA_7(w_mux_7.WR_DATA),
                .WR_SRAM_NUM_7(w_mux_7.WR_SRAM_NUM),
                .WR_EN_8(w_mux_8.WR_EN),
                .WR_ADDR_8(w_mux_8.WR_ADDR),
                .WR_DATA_8(w_mux_8.WR_DATA),
                .WR_SRAM_NUM_8(w_mux_8.WR_SRAM_NUM),
                .WR_EN_9(w_mux_9.WR_EN),
                .WR_ADDR_9(w_mux_9.WR_ADDR),
                .WR_DATA_9(w_mux_9.WR_DATA),
                .WR_SRAM_NUM_9(w_mux_9.WR_SRAM_NUM),
                .WR_EN_10(w_mux_10.WR_EN),
                .WR_ADDR_10(w_mux_10.WR_ADDR),
                .WR_DATA_10(w_mux_10.WR_DATA),
                .WR_SRAM_NUM_10(w_mux_10.WR_SRAM_NUM),
                .WR_EN_11(w_mux_11.WR_EN),
                .WR_ADDR_11(w_mux_11.WR_ADDR),
                .WR_DATA_11(w_mux_11.WR_DATA),
                .WR_SRAM_NUM_11(w_mux_11.WR_SRAM_NUM),
                .WR_EN_12(w_mux_12.WR_EN),
                .WR_ADDR_12(w_mux_12.WR_ADDR),
                .WR_DATA_12(w_mux_12.WR_DATA),
                .WR_SRAM_NUM_12(w_mux_12.WR_SRAM_NUM),
                .WR_EN_13(w_mux_13.WR_EN),
                .WR_ADDR_13(w_mux_13.WR_ADDR),
                .WR_DATA_13(w_mux_13.WR_DATA),
                .WR_SRAM_NUM_13(w_mux_13.WR_SRAM_NUM),
                .WR_EN_14(w_mux_14.WR_EN),
                .WR_ADDR_14(w_mux_14.WR_ADDR),
                .WR_DATA_14(w_mux_14.WR_DATA),
                .WR_SRAM_NUM_14(w_mux_14.WR_SRAM_NUM),
                .WR_EN_15(w_mux_15.WR_EN),
                .WR_ADDR_15(w_mux_15.WR_ADDR),
                .WR_DATA_15(w_mux_15.WR_DATA),
                .WR_SRAM_NUM_15(w_mux_15.WR_SRAM_NUM),
                .WR_EN_16(w_mux_16.WR_EN),
                .WR_ADDR_16(w_mux_16.WR_ADDR),
                .WR_DATA_16(w_mux_16.WR_DATA),
                .WR_SRAM_NUM_16(w_mux_16.WR_SRAM_NUM),
                .WR_EN_17(w_mux_17.WR_EN),
                .WR_ADDR_17(w_mux_17.WR_ADDR),
                .WR_DATA_17(w_mux_17.WR_DATA),
                .WR_SRAM_NUM_17(w_mux_17.WR_SRAM_NUM),
                .WR_EN_18(w_mux_18.WR_EN),
                .WR_ADDR_18(w_mux_18.WR_ADDR),
                .WR_DATA_18(w_mux_18.WR_DATA),
                .WR_SRAM_NUM_18(w_mux_18.WR_SRAM_NUM),
                .WR_EN_19(w_mux_19.WR_EN),
                .WR_ADDR_19(w_mux_19.WR_ADDR),
                .WR_DATA_19(w_mux_19.WR_DATA),
                .WR_SRAM_NUM_19(w_mux_19.WR_SRAM_NUM),
                .WR_EN_20(w_mux_20.WR_EN),
                .WR_ADDR_20(w_mux_20.WR_ADDR),
                .WR_DATA_20(w_mux_20.WR_DATA),
                .WR_SRAM_NUM_20(w_mux_20.WR_SRAM_NUM),
                .WR_EN_21(w_mux_21.WR_EN),
                .WR_ADDR_21(w_mux_21.WR_ADDR),
                .WR_DATA_21(w_mux_21.WR_DATA),
                .WR_SRAM_NUM_21(w_mux_21.WR_SRAM_NUM),
                .WR_EN_22(w_mux_22.WR_EN),
                .WR_ADDR_22(w_mux_22.WR_ADDR),
                .WR_DATA_22(w_mux_22.WR_DATA),
                .WR_SRAM_NUM_22(w_mux_22.WR_SRAM_NUM),
                .WR_EN_23(w_mux_23.WR_EN),
                .WR_ADDR_23(w_mux_23.WR_ADDR),
                .WR_DATA_23(w_mux_23.WR_DATA),
                .WR_SRAM_NUM_23(w_mux_23.WR_SRAM_NUM),
                .WR_EN_24(w_mux_24.WR_EN),
                .WR_ADDR_24(w_mux_24.WR_ADDR),
                .WR_DATA_24(w_mux_24.WR_DATA),
                .WR_SRAM_NUM_24(w_mux_24.WR_SRAM_NUM),
                .WR_EN_25(w_mux_25.WR_EN),
                .WR_ADDR_25(w_mux_25.WR_ADDR),
                .WR_DATA_25(w_mux_25.WR_DATA),
                .WR_SRAM_NUM_25(w_mux_25.WR_SRAM_NUM),
                .WR_EN_26(w_mux_26.WR_EN),
                .WR_ADDR_26(w_mux_26.WR_ADDR),
                .WR_DATA_26(w_mux_26.WR_DATA),
                .WR_SRAM_NUM_26(w_mux_26.WR_SRAM_NUM),
                .WR_EN_27(w_mux_27.WR_EN),
                .WR_ADDR_27(w_mux_27.WR_ADDR),
                .WR_DATA_27(w_mux_27.WR_DATA),
                .WR_SRAM_NUM_27(w_mux_27.WR_SRAM_NUM),
                .WR_EN_28(w_mux_28.WR_EN),
                .WR_ADDR_28(w_mux_28.WR_ADDR),
                .WR_DATA_28(w_mux_28.WR_DATA),
                .WR_SRAM_NUM_28(w_mux_28.WR_SRAM_NUM),
                .WR_EN_29(w_mux_29.WR_EN),
                .WR_ADDR_29(w_mux_29.WR_ADDR),
                .WR_DATA_29(w_mux_29.WR_DATA),
                .WR_SRAM_NUM_29(w_mux_29.WR_SRAM_NUM),
                .WR_EN_30(w_mux_30.WR_EN),
                .WR_ADDR_30(w_mux_30.WR_ADDR),
                .WR_DATA_30(w_mux_30.WR_DATA),
                .WR_SRAM_NUM_30(w_mux_30.WR_SRAM_NUM),
                .WR_EN_31(w_mux_31.WR_EN),
                .WR_ADDR_31(w_mux_31.WR_ADDR),
                .WR_DATA_31(w_mux_31.WR_DATA),
                .WR_SRAM_NUM_31(w_mux_31.WR_SRAM_NUM),
                .WR_EN_32(w_mux_32.WR_EN),
                .WR_ADDR_32(w_mux_32.WR_ADDR),
                .WR_DATA_32(w_mux_32.WR_DATA),
                .WR_SRAM_NUM_32(w_mux_32.WR_SRAM_NUM),
                .WR_EN_33(w_mux_33.WR_EN),
                .WR_ADDR_33(w_mux_33.WR_ADDR),
                .WR_DATA_33(w_mux_33.WR_DATA),
                .WR_SRAM_NUM_33(w_mux_33.WR_SRAM_NUM),
                .WR_EN_34(w_mux_34.WR_EN),
                .WR_ADDR_34(w_mux_34.WR_ADDR),
                .WR_DATA_34(w_mux_34.WR_DATA),
                .WR_SRAM_NUM_34(w_mux_34.WR_SRAM_NUM),
                .WR_EN_35(w_mux_35.WR_EN),
                .WR_ADDR_35(w_mux_35.WR_ADDR),
                .WR_DATA_35(w_mux_35.WR_DATA),
                .WR_SRAM_NUM_35(w_mux_35.WR_SRAM_NUM),
                .WR_EN_36(w_mux_36.WR_EN),
                .WR_ADDR_36(w_mux_36.WR_ADDR),
                .WR_DATA_36(w_mux_36.WR_DATA),
                .WR_SRAM_NUM_36(w_mux_36.WR_SRAM_NUM),
                .WR_EN_37(w_mux_37.WR_EN),
                .WR_ADDR_37(w_mux_37.WR_ADDR),
                .WR_DATA_37(w_mux_37.WR_DATA),
                .WR_SRAM_NUM_37(w_mux_37.WR_SRAM_NUM),
                .WR_EN_38(w_mux_38.WR_EN),
                .WR_ADDR_38(w_mux_38.WR_ADDR),
                .WR_DATA_38(w_mux_38.WR_DATA),
                .WR_SRAM_NUM_38(w_mux_38.WR_SRAM_NUM),
                .WR_EN_39(w_mux_39.WR_EN),
                .WR_ADDR_39(w_mux_39.WR_ADDR),
                .WR_DATA_39(w_mux_39.WR_DATA),
                .WR_SRAM_NUM_39(w_mux_39.WR_SRAM_NUM),
                .WR_EN_40(w_mux_40.WR_EN),
                .WR_ADDR_40(w_mux_40.WR_ADDR),
                .WR_DATA_40(w_mux_40.WR_DATA),
                .WR_SRAM_NUM_40(w_mux_40.WR_SRAM_NUM),
                .WR_EN_41(w_mux_41.WR_EN),
                .WR_ADDR_41(w_mux_41.WR_ADDR),
                .WR_DATA_41(w_mux_41.WR_DATA),
                .WR_SRAM_NUM_41(w_mux_41.WR_SRAM_NUM),
                .WR_EN_42(w_mux_42.WR_EN),
                .WR_ADDR_42(w_mux_42.WR_ADDR),
                .WR_DATA_42(w_mux_42.WR_DATA),
                .WR_SRAM_NUM_42(w_mux_42.WR_SRAM_NUM),
                .WR_EN_43(w_mux_43.WR_EN),
                .WR_ADDR_43(w_mux_43.WR_ADDR),
                .WR_DATA_43(w_mux_43.WR_DATA),
                .WR_SRAM_NUM_43(w_mux_43.WR_SRAM_NUM),
                .WR_EN_44(w_mux_44.WR_EN),
                .WR_ADDR_44(w_mux_44.WR_ADDR),
                .WR_DATA_44(w_mux_44.WR_DATA),
                .WR_SRAM_NUM_44(w_mux_44.WR_SRAM_NUM),
                .WR_EN_45(w_mux_45.WR_EN),
                .WR_ADDR_45(w_mux_45.WR_ADDR),
                .WR_DATA_45(w_mux_45.WR_DATA),
                .WR_SRAM_NUM_45(w_mux_45.WR_SRAM_NUM),
                .WR_EN_46(w_mux_46.WR_EN),
                .WR_ADDR_46(w_mux_46.WR_ADDR),
                .WR_DATA_46(w_mux_46.WR_DATA),
                .WR_SRAM_NUM_46(w_mux_46.WR_SRAM_NUM),
                .WR_EN_47(w_mux_47.WR_EN),
                .WR_ADDR_47(w_mux_47.WR_ADDR),
                .WR_DATA_47(w_mux_47.WR_DATA),
                .WR_SRAM_NUM_47(w_mux_47.WR_SRAM_NUM),
                .W_DATA(sram_mux_6.W_DATA),
                .W_ADDR(sram_mux_6.W_ADDR),
                .WR(sram_mux_6.WR)
            );
            wr_sram_ctrl#(.WR_SRAM_num(23))
            sram_ctrl_u_7(
                .WR_EN_0(w_mux_0.WR_EN),
                .WR_ADDR_0(w_mux_0.WR_ADDR),
                .WR_DATA_0(w_mux_0.WR_DATA),
                .WR_SRAM_NUM_0(w_mux_0.WR_SRAM_NUM),
                .WR_EN_1(w_mux_1.WR_EN),
                .WR_ADDR_1(w_mux_1.WR_ADDR),
                .WR_DATA_1(w_mux_1.WR_DATA),
                .WR_SRAM_NUM_1(w_mux_1.WR_SRAM_NUM),
                .WR_EN_2(w_mux_2.WR_EN),
                .WR_ADDR_2(w_mux_2.WR_ADDR),
                .WR_DATA_2(w_mux_2.WR_DATA),
                .WR_SRAM_NUM_2(w_mux_2.WR_SRAM_NUM),
                .WR_EN_3(w_mux_3.WR_EN),
                .WR_ADDR_3(w_mux_3.WR_ADDR),
                .WR_DATA_3(w_mux_3.WR_DATA),
                .WR_SRAM_NUM_3(w_mux_3.WR_SRAM_NUM),
                .WR_EN_4(w_mux_4.WR_EN),
                .WR_ADDR_4(w_mux_4.WR_ADDR),
                .WR_DATA_4(w_mux_4.WR_DATA),
                .WR_SRAM_NUM_4(w_mux_4.WR_SRAM_NUM),
                .WR_EN_5(w_mux_5.WR_EN),
                .WR_ADDR_5(w_mux_5.WR_ADDR),
                .WR_DATA_5(w_mux_5.WR_DATA),
                .WR_SRAM_NUM_5(w_mux_5.WR_SRAM_NUM),
                .WR_EN_6(w_mux_6.WR_EN),
                .WR_ADDR_6(w_mux_6.WR_ADDR),
                .WR_DATA_6(w_mux_6.WR_DATA),
                .WR_SRAM_NUM_6(w_mux_6.WR_SRAM_NUM),
                .WR_EN_7(w_mux_7.WR_EN),
                .WR_ADDR_7(w_mux_7.WR_ADDR),
                .WR_DATA_7(w_mux_7.WR_DATA),
                .WR_SRAM_NUM_7(w_mux_7.WR_SRAM_NUM),
                .WR_EN_8(w_mux_8.WR_EN),
                .WR_ADDR_8(w_mux_8.WR_ADDR),
                .WR_DATA_8(w_mux_8.WR_DATA),
                .WR_SRAM_NUM_8(w_mux_8.WR_SRAM_NUM),
                .WR_EN_9(w_mux_9.WR_EN),
                .WR_ADDR_9(w_mux_9.WR_ADDR),
                .WR_DATA_9(w_mux_9.WR_DATA),
                .WR_SRAM_NUM_9(w_mux_9.WR_SRAM_NUM),
                .WR_EN_10(w_mux_10.WR_EN),
                .WR_ADDR_10(w_mux_10.WR_ADDR),
                .WR_DATA_10(w_mux_10.WR_DATA),
                .WR_SRAM_NUM_10(w_mux_10.WR_SRAM_NUM),
                .WR_EN_11(w_mux_11.WR_EN),
                .WR_ADDR_11(w_mux_11.WR_ADDR),
                .WR_DATA_11(w_mux_11.WR_DATA),
                .WR_SRAM_NUM_11(w_mux_11.WR_SRAM_NUM),
                .WR_EN_12(w_mux_12.WR_EN),
                .WR_ADDR_12(w_mux_12.WR_ADDR),
                .WR_DATA_12(w_mux_12.WR_DATA),
                .WR_SRAM_NUM_12(w_mux_12.WR_SRAM_NUM),
                .WR_EN_13(w_mux_13.WR_EN),
                .WR_ADDR_13(w_mux_13.WR_ADDR),
                .WR_DATA_13(w_mux_13.WR_DATA),
                .WR_SRAM_NUM_13(w_mux_13.WR_SRAM_NUM),
                .WR_EN_14(w_mux_14.WR_EN),
                .WR_ADDR_14(w_mux_14.WR_ADDR),
                .WR_DATA_14(w_mux_14.WR_DATA),
                .WR_SRAM_NUM_14(w_mux_14.WR_SRAM_NUM),
                .WR_EN_15(w_mux_15.WR_EN),
                .WR_ADDR_15(w_mux_15.WR_ADDR),
                .WR_DATA_15(w_mux_15.WR_DATA),
                .WR_SRAM_NUM_15(w_mux_15.WR_SRAM_NUM),
                .WR_EN_16(w_mux_16.WR_EN),
                .WR_ADDR_16(w_mux_16.WR_ADDR),
                .WR_DATA_16(w_mux_16.WR_DATA),
                .WR_SRAM_NUM_16(w_mux_16.WR_SRAM_NUM),
                .WR_EN_17(w_mux_17.WR_EN),
                .WR_ADDR_17(w_mux_17.WR_ADDR),
                .WR_DATA_17(w_mux_17.WR_DATA),
                .WR_SRAM_NUM_17(w_mux_17.WR_SRAM_NUM),
                .WR_EN_18(w_mux_18.WR_EN),
                .WR_ADDR_18(w_mux_18.WR_ADDR),
                .WR_DATA_18(w_mux_18.WR_DATA),
                .WR_SRAM_NUM_18(w_mux_18.WR_SRAM_NUM),
                .WR_EN_19(w_mux_19.WR_EN),
                .WR_ADDR_19(w_mux_19.WR_ADDR),
                .WR_DATA_19(w_mux_19.WR_DATA),
                .WR_SRAM_NUM_19(w_mux_19.WR_SRAM_NUM),
                .WR_EN_20(w_mux_20.WR_EN),
                .WR_ADDR_20(w_mux_20.WR_ADDR),
                .WR_DATA_20(w_mux_20.WR_DATA),
                .WR_SRAM_NUM_20(w_mux_20.WR_SRAM_NUM),
                .WR_EN_21(w_mux_21.WR_EN),
                .WR_ADDR_21(w_mux_21.WR_ADDR),
                .WR_DATA_21(w_mux_21.WR_DATA),
                .WR_SRAM_NUM_21(w_mux_21.WR_SRAM_NUM),
                .WR_EN_22(w_mux_22.WR_EN),
                .WR_ADDR_22(w_mux_22.WR_ADDR),
                .WR_DATA_22(w_mux_22.WR_DATA),
                .WR_SRAM_NUM_22(w_mux_22.WR_SRAM_NUM),
                .WR_EN_23(w_mux_23.WR_EN),
                .WR_ADDR_23(w_mux_23.WR_ADDR),
                .WR_DATA_23(w_mux_23.WR_DATA),
                .WR_SRAM_NUM_23(w_mux_23.WR_SRAM_NUM),
                .WR_EN_24(w_mux_24.WR_EN),
                .WR_ADDR_24(w_mux_24.WR_ADDR),
                .WR_DATA_24(w_mux_24.WR_DATA),
                .WR_SRAM_NUM_24(w_mux_24.WR_SRAM_NUM),
                .WR_EN_25(w_mux_25.WR_EN),
                .WR_ADDR_25(w_mux_25.WR_ADDR),
                .WR_DATA_25(w_mux_25.WR_DATA),
                .WR_SRAM_NUM_25(w_mux_25.WR_SRAM_NUM),
                .WR_EN_26(w_mux_26.WR_EN),
                .WR_ADDR_26(w_mux_26.WR_ADDR),
                .WR_DATA_26(w_mux_26.WR_DATA),
                .WR_SRAM_NUM_26(w_mux_26.WR_SRAM_NUM),
                .WR_EN_27(w_mux_27.WR_EN),
                .WR_ADDR_27(w_mux_27.WR_ADDR),
                .WR_DATA_27(w_mux_27.WR_DATA),
                .WR_SRAM_NUM_27(w_mux_27.WR_SRAM_NUM),
                .WR_EN_28(w_mux_28.WR_EN),
                .WR_ADDR_28(w_mux_28.WR_ADDR),
                .WR_DATA_28(w_mux_28.WR_DATA),
                .WR_SRAM_NUM_28(w_mux_28.WR_SRAM_NUM),
                .WR_EN_29(w_mux_29.WR_EN),
                .WR_ADDR_29(w_mux_29.WR_ADDR),
                .WR_DATA_29(w_mux_29.WR_DATA),
                .WR_SRAM_NUM_29(w_mux_29.WR_SRAM_NUM),
                .WR_EN_30(w_mux_30.WR_EN),
                .WR_ADDR_30(w_mux_30.WR_ADDR),
                .WR_DATA_30(w_mux_30.WR_DATA),
                .WR_SRAM_NUM_30(w_mux_30.WR_SRAM_NUM),
                .WR_EN_31(w_mux_31.WR_EN),
                .WR_ADDR_31(w_mux_31.WR_ADDR),
                .WR_DATA_31(w_mux_31.WR_DATA),
                .WR_SRAM_NUM_31(w_mux_31.WR_SRAM_NUM),
                .WR_EN_32(w_mux_32.WR_EN),
                .WR_ADDR_32(w_mux_32.WR_ADDR),
                .WR_DATA_32(w_mux_32.WR_DATA),
                .WR_SRAM_NUM_32(w_mux_32.WR_SRAM_NUM),
                .WR_EN_33(w_mux_33.WR_EN),
                .WR_ADDR_33(w_mux_33.WR_ADDR),
                .WR_DATA_33(w_mux_33.WR_DATA),
                .WR_SRAM_NUM_33(w_mux_33.WR_SRAM_NUM),
                .WR_EN_34(w_mux_34.WR_EN),
                .WR_ADDR_34(w_mux_34.WR_ADDR),
                .WR_DATA_34(w_mux_34.WR_DATA),
                .WR_SRAM_NUM_34(w_mux_34.WR_SRAM_NUM),
                .WR_EN_35(w_mux_35.WR_EN),
                .WR_ADDR_35(w_mux_35.WR_ADDR),
                .WR_DATA_35(w_mux_35.WR_DATA),
                .WR_SRAM_NUM_35(w_mux_35.WR_SRAM_NUM),
                .WR_EN_36(w_mux_36.WR_EN),
                .WR_ADDR_36(w_mux_36.WR_ADDR),
                .WR_DATA_36(w_mux_36.WR_DATA),
                .WR_SRAM_NUM_36(w_mux_36.WR_SRAM_NUM),
                .WR_EN_37(w_mux_37.WR_EN),
                .WR_ADDR_37(w_mux_37.WR_ADDR),
                .WR_DATA_37(w_mux_37.WR_DATA),
                .WR_SRAM_NUM_37(w_mux_37.WR_SRAM_NUM),
                .WR_EN_38(w_mux_38.WR_EN),
                .WR_ADDR_38(w_mux_38.WR_ADDR),
                .WR_DATA_38(w_mux_38.WR_DATA),
                .WR_SRAM_NUM_38(w_mux_38.WR_SRAM_NUM),
                .WR_EN_39(w_mux_39.WR_EN),
                .WR_ADDR_39(w_mux_39.WR_ADDR),
                .WR_DATA_39(w_mux_39.WR_DATA),
                .WR_SRAM_NUM_39(w_mux_39.WR_SRAM_NUM),
                .WR_EN_40(w_mux_40.WR_EN),
                .WR_ADDR_40(w_mux_40.WR_ADDR),
                .WR_DATA_40(w_mux_40.WR_DATA),
                .WR_SRAM_NUM_40(w_mux_40.WR_SRAM_NUM),
                .WR_EN_41(w_mux_41.WR_EN),
                .WR_ADDR_41(w_mux_41.WR_ADDR),
                .WR_DATA_41(w_mux_41.WR_DATA),
                .WR_SRAM_NUM_41(w_mux_41.WR_SRAM_NUM),
                .WR_EN_42(w_mux_42.WR_EN),
                .WR_ADDR_42(w_mux_42.WR_ADDR),
                .WR_DATA_42(w_mux_42.WR_DATA),
                .WR_SRAM_NUM_42(w_mux_42.WR_SRAM_NUM),
                .WR_EN_43(w_mux_43.WR_EN),
                .WR_ADDR_43(w_mux_43.WR_ADDR),
                .WR_DATA_43(w_mux_43.WR_DATA),
                .WR_SRAM_NUM_43(w_mux_43.WR_SRAM_NUM),
                .WR_EN_44(w_mux_44.WR_EN),
                .WR_ADDR_44(w_mux_44.WR_ADDR),
                .WR_DATA_44(w_mux_44.WR_DATA),
                .WR_SRAM_NUM_44(w_mux_44.WR_SRAM_NUM),
                .WR_EN_45(w_mux_45.WR_EN),
                .WR_ADDR_45(w_mux_45.WR_ADDR),
                .WR_DATA_45(w_mux_45.WR_DATA),
                .WR_SRAM_NUM_45(w_mux_45.WR_SRAM_NUM),
                .WR_EN_46(w_mux_46.WR_EN),
                .WR_ADDR_46(w_mux_46.WR_ADDR),
                .WR_DATA_46(w_mux_46.WR_DATA),
                .WR_SRAM_NUM_46(w_mux_46.WR_SRAM_NUM),
                .WR_EN_47(w_mux_47.WR_EN),
                .WR_ADDR_47(w_mux_47.WR_ADDR),
                .WR_DATA_47(w_mux_47.WR_DATA),
                .WR_SRAM_NUM_47(w_mux_47.WR_SRAM_NUM),
                .W_DATA(sram_mux_7.W_DATA),
                .W_ADDR(sram_mux_7.W_ADDR),
                .WR(sram_mux_7.WR)
            );
            wr_sram_ctrl#(.WR_SRAM_num(24))
            sram_ctrl_u_8(
                .WR_EN_0(w_mux_0.WR_EN),
                .WR_ADDR_0(w_mux_0.WR_ADDR),
                .WR_DATA_0(w_mux_0.WR_DATA),
                .WR_SRAM_NUM_0(w_mux_0.WR_SRAM_NUM),
                .WR_EN_1(w_mux_1.WR_EN),
                .WR_ADDR_1(w_mux_1.WR_ADDR),
                .WR_DATA_1(w_mux_1.WR_DATA),
                .WR_SRAM_NUM_1(w_mux_1.WR_SRAM_NUM),
                .WR_EN_2(w_mux_2.WR_EN),
                .WR_ADDR_2(w_mux_2.WR_ADDR),
                .WR_DATA_2(w_mux_2.WR_DATA),
                .WR_SRAM_NUM_2(w_mux_2.WR_SRAM_NUM),
                .WR_EN_3(w_mux_3.WR_EN),
                .WR_ADDR_3(w_mux_3.WR_ADDR),
                .WR_DATA_3(w_mux_3.WR_DATA),
                .WR_SRAM_NUM_3(w_mux_3.WR_SRAM_NUM),
                .WR_EN_4(w_mux_4.WR_EN),
                .WR_ADDR_4(w_mux_4.WR_ADDR),
                .WR_DATA_4(w_mux_4.WR_DATA),
                .WR_SRAM_NUM_4(w_mux_4.WR_SRAM_NUM),
                .WR_EN_5(w_mux_5.WR_EN),
                .WR_ADDR_5(w_mux_5.WR_ADDR),
                .WR_DATA_5(w_mux_5.WR_DATA),
                .WR_SRAM_NUM_5(w_mux_5.WR_SRAM_NUM),
                .WR_EN_6(w_mux_6.WR_EN),
                .WR_ADDR_6(w_mux_6.WR_ADDR),
                .WR_DATA_6(w_mux_6.WR_DATA),
                .WR_SRAM_NUM_6(w_mux_6.WR_SRAM_NUM),
                .WR_EN_7(w_mux_7.WR_EN),
                .WR_ADDR_7(w_mux_7.WR_ADDR),
                .WR_DATA_7(w_mux_7.WR_DATA),
                .WR_SRAM_NUM_7(w_mux_7.WR_SRAM_NUM),
                .WR_EN_8(w_mux_8.WR_EN),
                .WR_ADDR_8(w_mux_8.WR_ADDR),
                .WR_DATA_8(w_mux_8.WR_DATA),
                .WR_SRAM_NUM_8(w_mux_8.WR_SRAM_NUM),
                .WR_EN_9(w_mux_9.WR_EN),
                .WR_ADDR_9(w_mux_9.WR_ADDR),
                .WR_DATA_9(w_mux_9.WR_DATA),
                .WR_SRAM_NUM_9(w_mux_9.WR_SRAM_NUM),
                .WR_EN_10(w_mux_10.WR_EN),
                .WR_ADDR_10(w_mux_10.WR_ADDR),
                .WR_DATA_10(w_mux_10.WR_DATA),
                .WR_SRAM_NUM_10(w_mux_10.WR_SRAM_NUM),
                .WR_EN_11(w_mux_11.WR_EN),
                .WR_ADDR_11(w_mux_11.WR_ADDR),
                .WR_DATA_11(w_mux_11.WR_DATA),
                .WR_SRAM_NUM_11(w_mux_11.WR_SRAM_NUM),
                .WR_EN_12(w_mux_12.WR_EN),
                .WR_ADDR_12(w_mux_12.WR_ADDR),
                .WR_DATA_12(w_mux_12.WR_DATA),
                .WR_SRAM_NUM_12(w_mux_12.WR_SRAM_NUM),
                .WR_EN_13(w_mux_13.WR_EN),
                .WR_ADDR_13(w_mux_13.WR_ADDR),
                .WR_DATA_13(w_mux_13.WR_DATA),
                .WR_SRAM_NUM_13(w_mux_13.WR_SRAM_NUM),
                .WR_EN_14(w_mux_14.WR_EN),
                .WR_ADDR_14(w_mux_14.WR_ADDR),
                .WR_DATA_14(w_mux_14.WR_DATA),
                .WR_SRAM_NUM_14(w_mux_14.WR_SRAM_NUM),
                .WR_EN_15(w_mux_15.WR_EN),
                .WR_ADDR_15(w_mux_15.WR_ADDR),
                .WR_DATA_15(w_mux_15.WR_DATA),
                .WR_SRAM_NUM_15(w_mux_15.WR_SRAM_NUM),
                .WR_EN_16(w_mux_16.WR_EN),
                .WR_ADDR_16(w_mux_16.WR_ADDR),
                .WR_DATA_16(w_mux_16.WR_DATA),
                .WR_SRAM_NUM_16(w_mux_16.WR_SRAM_NUM),
                .WR_EN_17(w_mux_17.WR_EN),
                .WR_ADDR_17(w_mux_17.WR_ADDR),
                .WR_DATA_17(w_mux_17.WR_DATA),
                .WR_SRAM_NUM_17(w_mux_17.WR_SRAM_NUM),
                .WR_EN_18(w_mux_18.WR_EN),
                .WR_ADDR_18(w_mux_18.WR_ADDR),
                .WR_DATA_18(w_mux_18.WR_DATA),
                .WR_SRAM_NUM_18(w_mux_18.WR_SRAM_NUM),
                .WR_EN_19(w_mux_19.WR_EN),
                .WR_ADDR_19(w_mux_19.WR_ADDR),
                .WR_DATA_19(w_mux_19.WR_DATA),
                .WR_SRAM_NUM_19(w_mux_19.WR_SRAM_NUM),
                .WR_EN_20(w_mux_20.WR_EN),
                .WR_ADDR_20(w_mux_20.WR_ADDR),
                .WR_DATA_20(w_mux_20.WR_DATA),
                .WR_SRAM_NUM_20(w_mux_20.WR_SRAM_NUM),
                .WR_EN_21(w_mux_21.WR_EN),
                .WR_ADDR_21(w_mux_21.WR_ADDR),
                .WR_DATA_21(w_mux_21.WR_DATA),
                .WR_SRAM_NUM_21(w_mux_21.WR_SRAM_NUM),
                .WR_EN_22(w_mux_22.WR_EN),
                .WR_ADDR_22(w_mux_22.WR_ADDR),
                .WR_DATA_22(w_mux_22.WR_DATA),
                .WR_SRAM_NUM_22(w_mux_22.WR_SRAM_NUM),
                .WR_EN_23(w_mux_23.WR_EN),
                .WR_ADDR_23(w_mux_23.WR_ADDR),
                .WR_DATA_23(w_mux_23.WR_DATA),
                .WR_SRAM_NUM_23(w_mux_23.WR_SRAM_NUM),
                .WR_EN_24(w_mux_24.WR_EN),
                .WR_ADDR_24(w_mux_24.WR_ADDR),
                .WR_DATA_24(w_mux_24.WR_DATA),
                .WR_SRAM_NUM_24(w_mux_24.WR_SRAM_NUM),
                .WR_EN_25(w_mux_25.WR_EN),
                .WR_ADDR_25(w_mux_25.WR_ADDR),
                .WR_DATA_25(w_mux_25.WR_DATA),
                .WR_SRAM_NUM_25(w_mux_25.WR_SRAM_NUM),
                .WR_EN_26(w_mux_26.WR_EN),
                .WR_ADDR_26(w_mux_26.WR_ADDR),
                .WR_DATA_26(w_mux_26.WR_DATA),
                .WR_SRAM_NUM_26(w_mux_26.WR_SRAM_NUM),
                .WR_EN_27(w_mux_27.WR_EN),
                .WR_ADDR_27(w_mux_27.WR_ADDR),
                .WR_DATA_27(w_mux_27.WR_DATA),
                .WR_SRAM_NUM_27(w_mux_27.WR_SRAM_NUM),
                .WR_EN_28(w_mux_28.WR_EN),
                .WR_ADDR_28(w_mux_28.WR_ADDR),
                .WR_DATA_28(w_mux_28.WR_DATA),
                .WR_SRAM_NUM_28(w_mux_28.WR_SRAM_NUM),
                .WR_EN_29(w_mux_29.WR_EN),
                .WR_ADDR_29(w_mux_29.WR_ADDR),
                .WR_DATA_29(w_mux_29.WR_DATA),
                .WR_SRAM_NUM_29(w_mux_29.WR_SRAM_NUM),
                .WR_EN_30(w_mux_30.WR_EN),
                .WR_ADDR_30(w_mux_30.WR_ADDR),
                .WR_DATA_30(w_mux_30.WR_DATA),
                .WR_SRAM_NUM_30(w_mux_30.WR_SRAM_NUM),
                .WR_EN_31(w_mux_31.WR_EN),
                .WR_ADDR_31(w_mux_31.WR_ADDR),
                .WR_DATA_31(w_mux_31.WR_DATA),
                .WR_SRAM_NUM_31(w_mux_31.WR_SRAM_NUM),
                .WR_EN_32(w_mux_32.WR_EN),
                .WR_ADDR_32(w_mux_32.WR_ADDR),
                .WR_DATA_32(w_mux_32.WR_DATA),
                .WR_SRAM_NUM_32(w_mux_32.WR_SRAM_NUM),
                .WR_EN_33(w_mux_33.WR_EN),
                .WR_ADDR_33(w_mux_33.WR_ADDR),
                .WR_DATA_33(w_mux_33.WR_DATA),
                .WR_SRAM_NUM_33(w_mux_33.WR_SRAM_NUM),
                .WR_EN_34(w_mux_34.WR_EN),
                .WR_ADDR_34(w_mux_34.WR_ADDR),
                .WR_DATA_34(w_mux_34.WR_DATA),
                .WR_SRAM_NUM_34(w_mux_34.WR_SRAM_NUM),
                .WR_EN_35(w_mux_35.WR_EN),
                .WR_ADDR_35(w_mux_35.WR_ADDR),
                .WR_DATA_35(w_mux_35.WR_DATA),
                .WR_SRAM_NUM_35(w_mux_35.WR_SRAM_NUM),
                .WR_EN_36(w_mux_36.WR_EN),
                .WR_ADDR_36(w_mux_36.WR_ADDR),
                .WR_DATA_36(w_mux_36.WR_DATA),
                .WR_SRAM_NUM_36(w_mux_36.WR_SRAM_NUM),
                .WR_EN_37(w_mux_37.WR_EN),
                .WR_ADDR_37(w_mux_37.WR_ADDR),
                .WR_DATA_37(w_mux_37.WR_DATA),
                .WR_SRAM_NUM_37(w_mux_37.WR_SRAM_NUM),
                .WR_EN_38(w_mux_38.WR_EN),
                .WR_ADDR_38(w_mux_38.WR_ADDR),
                .WR_DATA_38(w_mux_38.WR_DATA),
                .WR_SRAM_NUM_38(w_mux_38.WR_SRAM_NUM),
                .WR_EN_39(w_mux_39.WR_EN),
                .WR_ADDR_39(w_mux_39.WR_ADDR),
                .WR_DATA_39(w_mux_39.WR_DATA),
                .WR_SRAM_NUM_39(w_mux_39.WR_SRAM_NUM),
                .WR_EN_40(w_mux_40.WR_EN),
                .WR_ADDR_40(w_mux_40.WR_ADDR),
                .WR_DATA_40(w_mux_40.WR_DATA),
                .WR_SRAM_NUM_40(w_mux_40.WR_SRAM_NUM),
                .WR_EN_41(w_mux_41.WR_EN),
                .WR_ADDR_41(w_mux_41.WR_ADDR),
                .WR_DATA_41(w_mux_41.WR_DATA),
                .WR_SRAM_NUM_41(w_mux_41.WR_SRAM_NUM),
                .WR_EN_42(w_mux_42.WR_EN),
                .WR_ADDR_42(w_mux_42.WR_ADDR),
                .WR_DATA_42(w_mux_42.WR_DATA),
                .WR_SRAM_NUM_42(w_mux_42.WR_SRAM_NUM),
                .WR_EN_43(w_mux_43.WR_EN),
                .WR_ADDR_43(w_mux_43.WR_ADDR),
                .WR_DATA_43(w_mux_43.WR_DATA),
                .WR_SRAM_NUM_43(w_mux_43.WR_SRAM_NUM),
                .WR_EN_44(w_mux_44.WR_EN),
                .WR_ADDR_44(w_mux_44.WR_ADDR),
                .WR_DATA_44(w_mux_44.WR_DATA),
                .WR_SRAM_NUM_44(w_mux_44.WR_SRAM_NUM),
                .WR_EN_45(w_mux_45.WR_EN),
                .WR_ADDR_45(w_mux_45.WR_ADDR),
                .WR_DATA_45(w_mux_45.WR_DATA),
                .WR_SRAM_NUM_45(w_mux_45.WR_SRAM_NUM),
                .WR_EN_46(w_mux_46.WR_EN),
                .WR_ADDR_46(w_mux_46.WR_ADDR),
                .WR_DATA_46(w_mux_46.WR_DATA),
                .WR_SRAM_NUM_46(w_mux_46.WR_SRAM_NUM),
                .WR_EN_47(w_mux_47.WR_EN),
                .WR_ADDR_47(w_mux_47.WR_ADDR),
                .WR_DATA_47(w_mux_47.WR_DATA),
                .WR_SRAM_NUM_47(w_mux_47.WR_SRAM_NUM),
                .W_DATA(sram_mux_8.W_DATA),
                .W_ADDR(sram_mux_8.W_ADDR),
                .WR(sram_mux_8.WR)
            );
            wr_sram_ctrl#(.WR_SRAM_num(25))
            sram_ctrl_u_9(
                .WR_EN_0(w_mux_0.WR_EN),
                .WR_ADDR_0(w_mux_0.WR_ADDR),
                .WR_DATA_0(w_mux_0.WR_DATA),
                .WR_SRAM_NUM_0(w_mux_0.WR_SRAM_NUM),
                .WR_EN_1(w_mux_1.WR_EN),
                .WR_ADDR_1(w_mux_1.WR_ADDR),
                .WR_DATA_1(w_mux_1.WR_DATA),
                .WR_SRAM_NUM_1(w_mux_1.WR_SRAM_NUM),
                .WR_EN_2(w_mux_2.WR_EN),
                .WR_ADDR_2(w_mux_2.WR_ADDR),
                .WR_DATA_2(w_mux_2.WR_DATA),
                .WR_SRAM_NUM_2(w_mux_2.WR_SRAM_NUM),
                .WR_EN_3(w_mux_3.WR_EN),
                .WR_ADDR_3(w_mux_3.WR_ADDR),
                .WR_DATA_3(w_mux_3.WR_DATA),
                .WR_SRAM_NUM_3(w_mux_3.WR_SRAM_NUM),
                .WR_EN_4(w_mux_4.WR_EN),
                .WR_ADDR_4(w_mux_4.WR_ADDR),
                .WR_DATA_4(w_mux_4.WR_DATA),
                .WR_SRAM_NUM_4(w_mux_4.WR_SRAM_NUM),
                .WR_EN_5(w_mux_5.WR_EN),
                .WR_ADDR_5(w_mux_5.WR_ADDR),
                .WR_DATA_5(w_mux_5.WR_DATA),
                .WR_SRAM_NUM_5(w_mux_5.WR_SRAM_NUM),
                .WR_EN_6(w_mux_6.WR_EN),
                .WR_ADDR_6(w_mux_6.WR_ADDR),
                .WR_DATA_6(w_mux_6.WR_DATA),
                .WR_SRAM_NUM_6(w_mux_6.WR_SRAM_NUM),
                .WR_EN_7(w_mux_7.WR_EN),
                .WR_ADDR_7(w_mux_7.WR_ADDR),
                .WR_DATA_7(w_mux_7.WR_DATA),
                .WR_SRAM_NUM_7(w_mux_7.WR_SRAM_NUM),
                .WR_EN_8(w_mux_8.WR_EN),
                .WR_ADDR_8(w_mux_8.WR_ADDR),
                .WR_DATA_8(w_mux_8.WR_DATA),
                .WR_SRAM_NUM_8(w_mux_8.WR_SRAM_NUM),
                .WR_EN_9(w_mux_9.WR_EN),
                .WR_ADDR_9(w_mux_9.WR_ADDR),
                .WR_DATA_9(w_mux_9.WR_DATA),
                .WR_SRAM_NUM_9(w_mux_9.WR_SRAM_NUM),
                .WR_EN_10(w_mux_10.WR_EN),
                .WR_ADDR_10(w_mux_10.WR_ADDR),
                .WR_DATA_10(w_mux_10.WR_DATA),
                .WR_SRAM_NUM_10(w_mux_10.WR_SRAM_NUM),
                .WR_EN_11(w_mux_11.WR_EN),
                .WR_ADDR_11(w_mux_11.WR_ADDR),
                .WR_DATA_11(w_mux_11.WR_DATA),
                .WR_SRAM_NUM_11(w_mux_11.WR_SRAM_NUM),
                .WR_EN_12(w_mux_12.WR_EN),
                .WR_ADDR_12(w_mux_12.WR_ADDR),
                .WR_DATA_12(w_mux_12.WR_DATA),
                .WR_SRAM_NUM_12(w_mux_12.WR_SRAM_NUM),
                .WR_EN_13(w_mux_13.WR_EN),
                .WR_ADDR_13(w_mux_13.WR_ADDR),
                .WR_DATA_13(w_mux_13.WR_DATA),
                .WR_SRAM_NUM_13(w_mux_13.WR_SRAM_NUM),
                .WR_EN_14(w_mux_14.WR_EN),
                .WR_ADDR_14(w_mux_14.WR_ADDR),
                .WR_DATA_14(w_mux_14.WR_DATA),
                .WR_SRAM_NUM_14(w_mux_14.WR_SRAM_NUM),
                .WR_EN_15(w_mux_15.WR_EN),
                .WR_ADDR_15(w_mux_15.WR_ADDR),
                .WR_DATA_15(w_mux_15.WR_DATA),
                .WR_SRAM_NUM_15(w_mux_15.WR_SRAM_NUM),
                .WR_EN_16(w_mux_16.WR_EN),
                .WR_ADDR_16(w_mux_16.WR_ADDR),
                .WR_DATA_16(w_mux_16.WR_DATA),
                .WR_SRAM_NUM_16(w_mux_16.WR_SRAM_NUM),
                .WR_EN_17(w_mux_17.WR_EN),
                .WR_ADDR_17(w_mux_17.WR_ADDR),
                .WR_DATA_17(w_mux_17.WR_DATA),
                .WR_SRAM_NUM_17(w_mux_17.WR_SRAM_NUM),
                .WR_EN_18(w_mux_18.WR_EN),
                .WR_ADDR_18(w_mux_18.WR_ADDR),
                .WR_DATA_18(w_mux_18.WR_DATA),
                .WR_SRAM_NUM_18(w_mux_18.WR_SRAM_NUM),
                .WR_EN_19(w_mux_19.WR_EN),
                .WR_ADDR_19(w_mux_19.WR_ADDR),
                .WR_DATA_19(w_mux_19.WR_DATA),
                .WR_SRAM_NUM_19(w_mux_19.WR_SRAM_NUM),
                .WR_EN_20(w_mux_20.WR_EN),
                .WR_ADDR_20(w_mux_20.WR_ADDR),
                .WR_DATA_20(w_mux_20.WR_DATA),
                .WR_SRAM_NUM_20(w_mux_20.WR_SRAM_NUM),
                .WR_EN_21(w_mux_21.WR_EN),
                .WR_ADDR_21(w_mux_21.WR_ADDR),
                .WR_DATA_21(w_mux_21.WR_DATA),
                .WR_SRAM_NUM_21(w_mux_21.WR_SRAM_NUM),
                .WR_EN_22(w_mux_22.WR_EN),
                .WR_ADDR_22(w_mux_22.WR_ADDR),
                .WR_DATA_22(w_mux_22.WR_DATA),
                .WR_SRAM_NUM_22(w_mux_22.WR_SRAM_NUM),
                .WR_EN_23(w_mux_23.WR_EN),
                .WR_ADDR_23(w_mux_23.WR_ADDR),
                .WR_DATA_23(w_mux_23.WR_DATA),
                .WR_SRAM_NUM_23(w_mux_23.WR_SRAM_NUM),
                .WR_EN_24(w_mux_24.WR_EN),
                .WR_ADDR_24(w_mux_24.WR_ADDR),
                .WR_DATA_24(w_mux_24.WR_DATA),
                .WR_SRAM_NUM_24(w_mux_24.WR_SRAM_NUM),
                .WR_EN_25(w_mux_25.WR_EN),
                .WR_ADDR_25(w_mux_25.WR_ADDR),
                .WR_DATA_25(w_mux_25.WR_DATA),
                .WR_SRAM_NUM_25(w_mux_25.WR_SRAM_NUM),
                .WR_EN_26(w_mux_26.WR_EN),
                .WR_ADDR_26(w_mux_26.WR_ADDR),
                .WR_DATA_26(w_mux_26.WR_DATA),
                .WR_SRAM_NUM_26(w_mux_26.WR_SRAM_NUM),
                .WR_EN_27(w_mux_27.WR_EN),
                .WR_ADDR_27(w_mux_27.WR_ADDR),
                .WR_DATA_27(w_mux_27.WR_DATA),
                .WR_SRAM_NUM_27(w_mux_27.WR_SRAM_NUM),
                .WR_EN_28(w_mux_28.WR_EN),
                .WR_ADDR_28(w_mux_28.WR_ADDR),
                .WR_DATA_28(w_mux_28.WR_DATA),
                .WR_SRAM_NUM_28(w_mux_28.WR_SRAM_NUM),
                .WR_EN_29(w_mux_29.WR_EN),
                .WR_ADDR_29(w_mux_29.WR_ADDR),
                .WR_DATA_29(w_mux_29.WR_DATA),
                .WR_SRAM_NUM_29(w_mux_29.WR_SRAM_NUM),
                .WR_EN_30(w_mux_30.WR_EN),
                .WR_ADDR_30(w_mux_30.WR_ADDR),
                .WR_DATA_30(w_mux_30.WR_DATA),
                .WR_SRAM_NUM_30(w_mux_30.WR_SRAM_NUM),
                .WR_EN_31(w_mux_31.WR_EN),
                .WR_ADDR_31(w_mux_31.WR_ADDR),
                .WR_DATA_31(w_mux_31.WR_DATA),
                .WR_SRAM_NUM_31(w_mux_31.WR_SRAM_NUM),
                .WR_EN_32(w_mux_32.WR_EN),
                .WR_ADDR_32(w_mux_32.WR_ADDR),
                .WR_DATA_32(w_mux_32.WR_DATA),
                .WR_SRAM_NUM_32(w_mux_32.WR_SRAM_NUM),
                .WR_EN_33(w_mux_33.WR_EN),
                .WR_ADDR_33(w_mux_33.WR_ADDR),
                .WR_DATA_33(w_mux_33.WR_DATA),
                .WR_SRAM_NUM_33(w_mux_33.WR_SRAM_NUM),
                .WR_EN_34(w_mux_34.WR_EN),
                .WR_ADDR_34(w_mux_34.WR_ADDR),
                .WR_DATA_34(w_mux_34.WR_DATA),
                .WR_SRAM_NUM_34(w_mux_34.WR_SRAM_NUM),
                .WR_EN_35(w_mux_35.WR_EN),
                .WR_ADDR_35(w_mux_35.WR_ADDR),
                .WR_DATA_35(w_mux_35.WR_DATA),
                .WR_SRAM_NUM_35(w_mux_35.WR_SRAM_NUM),
                .WR_EN_36(w_mux_36.WR_EN),
                .WR_ADDR_36(w_mux_36.WR_ADDR),
                .WR_DATA_36(w_mux_36.WR_DATA),
                .WR_SRAM_NUM_36(w_mux_36.WR_SRAM_NUM),
                .WR_EN_37(w_mux_37.WR_EN),
                .WR_ADDR_37(w_mux_37.WR_ADDR),
                .WR_DATA_37(w_mux_37.WR_DATA),
                .WR_SRAM_NUM_37(w_mux_37.WR_SRAM_NUM),
                .WR_EN_38(w_mux_38.WR_EN),
                .WR_ADDR_38(w_mux_38.WR_ADDR),
                .WR_DATA_38(w_mux_38.WR_DATA),
                .WR_SRAM_NUM_38(w_mux_38.WR_SRAM_NUM),
                .WR_EN_39(w_mux_39.WR_EN),
                .WR_ADDR_39(w_mux_39.WR_ADDR),
                .WR_DATA_39(w_mux_39.WR_DATA),
                .WR_SRAM_NUM_39(w_mux_39.WR_SRAM_NUM),
                .WR_EN_40(w_mux_40.WR_EN),
                .WR_ADDR_40(w_mux_40.WR_ADDR),
                .WR_DATA_40(w_mux_40.WR_DATA),
                .WR_SRAM_NUM_40(w_mux_40.WR_SRAM_NUM),
                .WR_EN_41(w_mux_41.WR_EN),
                .WR_ADDR_41(w_mux_41.WR_ADDR),
                .WR_DATA_41(w_mux_41.WR_DATA),
                .WR_SRAM_NUM_41(w_mux_41.WR_SRAM_NUM),
                .WR_EN_42(w_mux_42.WR_EN),
                .WR_ADDR_42(w_mux_42.WR_ADDR),
                .WR_DATA_42(w_mux_42.WR_DATA),
                .WR_SRAM_NUM_42(w_mux_42.WR_SRAM_NUM),
                .WR_EN_43(w_mux_43.WR_EN),
                .WR_ADDR_43(w_mux_43.WR_ADDR),
                .WR_DATA_43(w_mux_43.WR_DATA),
                .WR_SRAM_NUM_43(w_mux_43.WR_SRAM_NUM),
                .WR_EN_44(w_mux_44.WR_EN),
                .WR_ADDR_44(w_mux_44.WR_ADDR),
                .WR_DATA_44(w_mux_44.WR_DATA),
                .WR_SRAM_NUM_44(w_mux_44.WR_SRAM_NUM),
                .WR_EN_45(w_mux_45.WR_EN),
                .WR_ADDR_45(w_mux_45.WR_ADDR),
                .WR_DATA_45(w_mux_45.WR_DATA),
                .WR_SRAM_NUM_45(w_mux_45.WR_SRAM_NUM),
                .WR_EN_46(w_mux_46.WR_EN),
                .WR_ADDR_46(w_mux_46.WR_ADDR),
                .WR_DATA_46(w_mux_46.WR_DATA),
                .WR_SRAM_NUM_46(w_mux_46.WR_SRAM_NUM),
                .WR_EN_47(w_mux_47.WR_EN),
                .WR_ADDR_47(w_mux_47.WR_ADDR),
                .WR_DATA_47(w_mux_47.WR_DATA),
                .WR_SRAM_NUM_47(w_mux_47.WR_SRAM_NUM),
                .W_DATA(sram_mux_9.W_DATA),
                .W_ADDR(sram_mux_9.W_ADDR),
                .WR(sram_mux_9.WR)
            );
            wr_sram_ctrl#(.WR_SRAM_num(26))
            sram_ctrl_u_10(
                .WR_EN_0(w_mux_0.WR_EN),
                .WR_ADDR_0(w_mux_0.WR_ADDR),
                .WR_DATA_0(w_mux_0.WR_DATA),
                .WR_SRAM_NUM_0(w_mux_0.WR_SRAM_NUM),
                .WR_EN_1(w_mux_1.WR_EN),
                .WR_ADDR_1(w_mux_1.WR_ADDR),
                .WR_DATA_1(w_mux_1.WR_DATA),
                .WR_SRAM_NUM_1(w_mux_1.WR_SRAM_NUM),
                .WR_EN_2(w_mux_2.WR_EN),
                .WR_ADDR_2(w_mux_2.WR_ADDR),
                .WR_DATA_2(w_mux_2.WR_DATA),
                .WR_SRAM_NUM_2(w_mux_2.WR_SRAM_NUM),
                .WR_EN_3(w_mux_3.WR_EN),
                .WR_ADDR_3(w_mux_3.WR_ADDR),
                .WR_DATA_3(w_mux_3.WR_DATA),
                .WR_SRAM_NUM_3(w_mux_3.WR_SRAM_NUM),
                .WR_EN_4(w_mux_4.WR_EN),
                .WR_ADDR_4(w_mux_4.WR_ADDR),
                .WR_DATA_4(w_mux_4.WR_DATA),
                .WR_SRAM_NUM_4(w_mux_4.WR_SRAM_NUM),
                .WR_EN_5(w_mux_5.WR_EN),
                .WR_ADDR_5(w_mux_5.WR_ADDR),
                .WR_DATA_5(w_mux_5.WR_DATA),
                .WR_SRAM_NUM_5(w_mux_5.WR_SRAM_NUM),
                .WR_EN_6(w_mux_6.WR_EN),
                .WR_ADDR_6(w_mux_6.WR_ADDR),
                .WR_DATA_6(w_mux_6.WR_DATA),
                .WR_SRAM_NUM_6(w_mux_6.WR_SRAM_NUM),
                .WR_EN_7(w_mux_7.WR_EN),
                .WR_ADDR_7(w_mux_7.WR_ADDR),
                .WR_DATA_7(w_mux_7.WR_DATA),
                .WR_SRAM_NUM_7(w_mux_7.WR_SRAM_NUM),
                .WR_EN_8(w_mux_8.WR_EN),
                .WR_ADDR_8(w_mux_8.WR_ADDR),
                .WR_DATA_8(w_mux_8.WR_DATA),
                .WR_SRAM_NUM_8(w_mux_8.WR_SRAM_NUM),
                .WR_EN_9(w_mux_9.WR_EN),
                .WR_ADDR_9(w_mux_9.WR_ADDR),
                .WR_DATA_9(w_mux_9.WR_DATA),
                .WR_SRAM_NUM_9(w_mux_9.WR_SRAM_NUM),
                .WR_EN_10(w_mux_10.WR_EN),
                .WR_ADDR_10(w_mux_10.WR_ADDR),
                .WR_DATA_10(w_mux_10.WR_DATA),
                .WR_SRAM_NUM_10(w_mux_10.WR_SRAM_NUM),
                .WR_EN_11(w_mux_11.WR_EN),
                .WR_ADDR_11(w_mux_11.WR_ADDR),
                .WR_DATA_11(w_mux_11.WR_DATA),
                .WR_SRAM_NUM_11(w_mux_11.WR_SRAM_NUM),
                .WR_EN_12(w_mux_12.WR_EN),
                .WR_ADDR_12(w_mux_12.WR_ADDR),
                .WR_DATA_12(w_mux_12.WR_DATA),
                .WR_SRAM_NUM_12(w_mux_12.WR_SRAM_NUM),
                .WR_EN_13(w_mux_13.WR_EN),
                .WR_ADDR_13(w_mux_13.WR_ADDR),
                .WR_DATA_13(w_mux_13.WR_DATA),
                .WR_SRAM_NUM_13(w_mux_13.WR_SRAM_NUM),
                .WR_EN_14(w_mux_14.WR_EN),
                .WR_ADDR_14(w_mux_14.WR_ADDR),
                .WR_DATA_14(w_mux_14.WR_DATA),
                .WR_SRAM_NUM_14(w_mux_14.WR_SRAM_NUM),
                .WR_EN_15(w_mux_15.WR_EN),
                .WR_ADDR_15(w_mux_15.WR_ADDR),
                .WR_DATA_15(w_mux_15.WR_DATA),
                .WR_SRAM_NUM_15(w_mux_15.WR_SRAM_NUM),
                .WR_EN_16(w_mux_16.WR_EN),
                .WR_ADDR_16(w_mux_16.WR_ADDR),
                .WR_DATA_16(w_mux_16.WR_DATA),
                .WR_SRAM_NUM_16(w_mux_16.WR_SRAM_NUM),
                .WR_EN_17(w_mux_17.WR_EN),
                .WR_ADDR_17(w_mux_17.WR_ADDR),
                .WR_DATA_17(w_mux_17.WR_DATA),
                .WR_SRAM_NUM_17(w_mux_17.WR_SRAM_NUM),
                .WR_EN_18(w_mux_18.WR_EN),
                .WR_ADDR_18(w_mux_18.WR_ADDR),
                .WR_DATA_18(w_mux_18.WR_DATA),
                .WR_SRAM_NUM_18(w_mux_18.WR_SRAM_NUM),
                .WR_EN_19(w_mux_19.WR_EN),
                .WR_ADDR_19(w_mux_19.WR_ADDR),
                .WR_DATA_19(w_mux_19.WR_DATA),
                .WR_SRAM_NUM_19(w_mux_19.WR_SRAM_NUM),
                .WR_EN_20(w_mux_20.WR_EN),
                .WR_ADDR_20(w_mux_20.WR_ADDR),
                .WR_DATA_20(w_mux_20.WR_DATA),
                .WR_SRAM_NUM_20(w_mux_20.WR_SRAM_NUM),
                .WR_EN_21(w_mux_21.WR_EN),
                .WR_ADDR_21(w_mux_21.WR_ADDR),
                .WR_DATA_21(w_mux_21.WR_DATA),
                .WR_SRAM_NUM_21(w_mux_21.WR_SRAM_NUM),
                .WR_EN_22(w_mux_22.WR_EN),
                .WR_ADDR_22(w_mux_22.WR_ADDR),
                .WR_DATA_22(w_mux_22.WR_DATA),
                .WR_SRAM_NUM_22(w_mux_22.WR_SRAM_NUM),
                .WR_EN_23(w_mux_23.WR_EN),
                .WR_ADDR_23(w_mux_23.WR_ADDR),
                .WR_DATA_23(w_mux_23.WR_DATA),
                .WR_SRAM_NUM_23(w_mux_23.WR_SRAM_NUM),
                .WR_EN_24(w_mux_24.WR_EN),
                .WR_ADDR_24(w_mux_24.WR_ADDR),
                .WR_DATA_24(w_mux_24.WR_DATA),
                .WR_SRAM_NUM_24(w_mux_24.WR_SRAM_NUM),
                .WR_EN_25(w_mux_25.WR_EN),
                .WR_ADDR_25(w_mux_25.WR_ADDR),
                .WR_DATA_25(w_mux_25.WR_DATA),
                .WR_SRAM_NUM_25(w_mux_25.WR_SRAM_NUM),
                .WR_EN_26(w_mux_26.WR_EN),
                .WR_ADDR_26(w_mux_26.WR_ADDR),
                .WR_DATA_26(w_mux_26.WR_DATA),
                .WR_SRAM_NUM_26(w_mux_26.WR_SRAM_NUM),
                .WR_EN_27(w_mux_27.WR_EN),
                .WR_ADDR_27(w_mux_27.WR_ADDR),
                .WR_DATA_27(w_mux_27.WR_DATA),
                .WR_SRAM_NUM_27(w_mux_27.WR_SRAM_NUM),
                .WR_EN_28(w_mux_28.WR_EN),
                .WR_ADDR_28(w_mux_28.WR_ADDR),
                .WR_DATA_28(w_mux_28.WR_DATA),
                .WR_SRAM_NUM_28(w_mux_28.WR_SRAM_NUM),
                .WR_EN_29(w_mux_29.WR_EN),
                .WR_ADDR_29(w_mux_29.WR_ADDR),
                .WR_DATA_29(w_mux_29.WR_DATA),
                .WR_SRAM_NUM_29(w_mux_29.WR_SRAM_NUM),
                .WR_EN_30(w_mux_30.WR_EN),
                .WR_ADDR_30(w_mux_30.WR_ADDR),
                .WR_DATA_30(w_mux_30.WR_DATA),
                .WR_SRAM_NUM_30(w_mux_30.WR_SRAM_NUM),
                .WR_EN_31(w_mux_31.WR_EN),
                .WR_ADDR_31(w_mux_31.WR_ADDR),
                .WR_DATA_31(w_mux_31.WR_DATA),
                .WR_SRAM_NUM_31(w_mux_31.WR_SRAM_NUM),
                .WR_EN_32(w_mux_32.WR_EN),
                .WR_ADDR_32(w_mux_32.WR_ADDR),
                .WR_DATA_32(w_mux_32.WR_DATA),
                .WR_SRAM_NUM_32(w_mux_32.WR_SRAM_NUM),
                .WR_EN_33(w_mux_33.WR_EN),
                .WR_ADDR_33(w_mux_33.WR_ADDR),
                .WR_DATA_33(w_mux_33.WR_DATA),
                .WR_SRAM_NUM_33(w_mux_33.WR_SRAM_NUM),
                .WR_EN_34(w_mux_34.WR_EN),
                .WR_ADDR_34(w_mux_34.WR_ADDR),
                .WR_DATA_34(w_mux_34.WR_DATA),
                .WR_SRAM_NUM_34(w_mux_34.WR_SRAM_NUM),
                .WR_EN_35(w_mux_35.WR_EN),
                .WR_ADDR_35(w_mux_35.WR_ADDR),
                .WR_DATA_35(w_mux_35.WR_DATA),
                .WR_SRAM_NUM_35(w_mux_35.WR_SRAM_NUM),
                .WR_EN_36(w_mux_36.WR_EN),
                .WR_ADDR_36(w_mux_36.WR_ADDR),
                .WR_DATA_36(w_mux_36.WR_DATA),
                .WR_SRAM_NUM_36(w_mux_36.WR_SRAM_NUM),
                .WR_EN_37(w_mux_37.WR_EN),
                .WR_ADDR_37(w_mux_37.WR_ADDR),
                .WR_DATA_37(w_mux_37.WR_DATA),
                .WR_SRAM_NUM_37(w_mux_37.WR_SRAM_NUM),
                .WR_EN_38(w_mux_38.WR_EN),
                .WR_ADDR_38(w_mux_38.WR_ADDR),
                .WR_DATA_38(w_mux_38.WR_DATA),
                .WR_SRAM_NUM_38(w_mux_38.WR_SRAM_NUM),
                .WR_EN_39(w_mux_39.WR_EN),
                .WR_ADDR_39(w_mux_39.WR_ADDR),
                .WR_DATA_39(w_mux_39.WR_DATA),
                .WR_SRAM_NUM_39(w_mux_39.WR_SRAM_NUM),
                .WR_EN_40(w_mux_40.WR_EN),
                .WR_ADDR_40(w_mux_40.WR_ADDR),
                .WR_DATA_40(w_mux_40.WR_DATA),
                .WR_SRAM_NUM_40(w_mux_40.WR_SRAM_NUM),
                .WR_EN_41(w_mux_41.WR_EN),
                .WR_ADDR_41(w_mux_41.WR_ADDR),
                .WR_DATA_41(w_mux_41.WR_DATA),
                .WR_SRAM_NUM_41(w_mux_41.WR_SRAM_NUM),
                .WR_EN_42(w_mux_42.WR_EN),
                .WR_ADDR_42(w_mux_42.WR_ADDR),
                .WR_DATA_42(w_mux_42.WR_DATA),
                .WR_SRAM_NUM_42(w_mux_42.WR_SRAM_NUM),
                .WR_EN_43(w_mux_43.WR_EN),
                .WR_ADDR_43(w_mux_43.WR_ADDR),
                .WR_DATA_43(w_mux_43.WR_DATA),
                .WR_SRAM_NUM_43(w_mux_43.WR_SRAM_NUM),
                .WR_EN_44(w_mux_44.WR_EN),
                .WR_ADDR_44(w_mux_44.WR_ADDR),
                .WR_DATA_44(w_mux_44.WR_DATA),
                .WR_SRAM_NUM_44(w_mux_44.WR_SRAM_NUM),
                .WR_EN_45(w_mux_45.WR_EN),
                .WR_ADDR_45(w_mux_45.WR_ADDR),
                .WR_DATA_45(w_mux_45.WR_DATA),
                .WR_SRAM_NUM_45(w_mux_45.WR_SRAM_NUM),
                .WR_EN_46(w_mux_46.WR_EN),
                .WR_ADDR_46(w_mux_46.WR_ADDR),
                .WR_DATA_46(w_mux_46.WR_DATA),
                .WR_SRAM_NUM_46(w_mux_46.WR_SRAM_NUM),
                .WR_EN_47(w_mux_47.WR_EN),
                .WR_ADDR_47(w_mux_47.WR_ADDR),
                .WR_DATA_47(w_mux_47.WR_DATA),
                .WR_SRAM_NUM_47(w_mux_47.WR_SRAM_NUM),
                .W_DATA(sram_mux_10.W_DATA),
                .W_ADDR(sram_mux_10.W_ADDR),
                .WR(sram_mux_10.WR)
            );
            wr_sram_ctrl#(.WR_SRAM_num(27))
            sram_ctrl_u_11(
                .WR_EN_0(w_mux_0.WR_EN),
                .WR_ADDR_0(w_mux_0.WR_ADDR),
                .WR_DATA_0(w_mux_0.WR_DATA),
                .WR_SRAM_NUM_0(w_mux_0.WR_SRAM_NUM),
                .WR_EN_1(w_mux_1.WR_EN),
                .WR_ADDR_1(w_mux_1.WR_ADDR),
                .WR_DATA_1(w_mux_1.WR_DATA),
                .WR_SRAM_NUM_1(w_mux_1.WR_SRAM_NUM),
                .WR_EN_2(w_mux_2.WR_EN),
                .WR_ADDR_2(w_mux_2.WR_ADDR),
                .WR_DATA_2(w_mux_2.WR_DATA),
                .WR_SRAM_NUM_2(w_mux_2.WR_SRAM_NUM),
                .WR_EN_3(w_mux_3.WR_EN),
                .WR_ADDR_3(w_mux_3.WR_ADDR),
                .WR_DATA_3(w_mux_3.WR_DATA),
                .WR_SRAM_NUM_3(w_mux_3.WR_SRAM_NUM),
                .WR_EN_4(w_mux_4.WR_EN),
                .WR_ADDR_4(w_mux_4.WR_ADDR),
                .WR_DATA_4(w_mux_4.WR_DATA),
                .WR_SRAM_NUM_4(w_mux_4.WR_SRAM_NUM),
                .WR_EN_5(w_mux_5.WR_EN),
                .WR_ADDR_5(w_mux_5.WR_ADDR),
                .WR_DATA_5(w_mux_5.WR_DATA),
                .WR_SRAM_NUM_5(w_mux_5.WR_SRAM_NUM),
                .WR_EN_6(w_mux_6.WR_EN),
                .WR_ADDR_6(w_mux_6.WR_ADDR),
                .WR_DATA_6(w_mux_6.WR_DATA),
                .WR_SRAM_NUM_6(w_mux_6.WR_SRAM_NUM),
                .WR_EN_7(w_mux_7.WR_EN),
                .WR_ADDR_7(w_mux_7.WR_ADDR),
                .WR_DATA_7(w_mux_7.WR_DATA),
                .WR_SRAM_NUM_7(w_mux_7.WR_SRAM_NUM),
                .WR_EN_8(w_mux_8.WR_EN),
                .WR_ADDR_8(w_mux_8.WR_ADDR),
                .WR_DATA_8(w_mux_8.WR_DATA),
                .WR_SRAM_NUM_8(w_mux_8.WR_SRAM_NUM),
                .WR_EN_9(w_mux_9.WR_EN),
                .WR_ADDR_9(w_mux_9.WR_ADDR),
                .WR_DATA_9(w_mux_9.WR_DATA),
                .WR_SRAM_NUM_9(w_mux_9.WR_SRAM_NUM),
                .WR_EN_10(w_mux_10.WR_EN),
                .WR_ADDR_10(w_mux_10.WR_ADDR),
                .WR_DATA_10(w_mux_10.WR_DATA),
                .WR_SRAM_NUM_10(w_mux_10.WR_SRAM_NUM),
                .WR_EN_11(w_mux_11.WR_EN),
                .WR_ADDR_11(w_mux_11.WR_ADDR),
                .WR_DATA_11(w_mux_11.WR_DATA),
                .WR_SRAM_NUM_11(w_mux_11.WR_SRAM_NUM),
                .WR_EN_12(w_mux_12.WR_EN),
                .WR_ADDR_12(w_mux_12.WR_ADDR),
                .WR_DATA_12(w_mux_12.WR_DATA),
                .WR_SRAM_NUM_12(w_mux_12.WR_SRAM_NUM),
                .WR_EN_13(w_mux_13.WR_EN),
                .WR_ADDR_13(w_mux_13.WR_ADDR),
                .WR_DATA_13(w_mux_13.WR_DATA),
                .WR_SRAM_NUM_13(w_mux_13.WR_SRAM_NUM),
                .WR_EN_14(w_mux_14.WR_EN),
                .WR_ADDR_14(w_mux_14.WR_ADDR),
                .WR_DATA_14(w_mux_14.WR_DATA),
                .WR_SRAM_NUM_14(w_mux_14.WR_SRAM_NUM),
                .WR_EN_15(w_mux_15.WR_EN),
                .WR_ADDR_15(w_mux_15.WR_ADDR),
                .WR_DATA_15(w_mux_15.WR_DATA),
                .WR_SRAM_NUM_15(w_mux_15.WR_SRAM_NUM),
                .WR_EN_16(w_mux_16.WR_EN),
                .WR_ADDR_16(w_mux_16.WR_ADDR),
                .WR_DATA_16(w_mux_16.WR_DATA),
                .WR_SRAM_NUM_16(w_mux_16.WR_SRAM_NUM),
                .WR_EN_17(w_mux_17.WR_EN),
                .WR_ADDR_17(w_mux_17.WR_ADDR),
                .WR_DATA_17(w_mux_17.WR_DATA),
                .WR_SRAM_NUM_17(w_mux_17.WR_SRAM_NUM),
                .WR_EN_18(w_mux_18.WR_EN),
                .WR_ADDR_18(w_mux_18.WR_ADDR),
                .WR_DATA_18(w_mux_18.WR_DATA),
                .WR_SRAM_NUM_18(w_mux_18.WR_SRAM_NUM),
                .WR_EN_19(w_mux_19.WR_EN),
                .WR_ADDR_19(w_mux_19.WR_ADDR),
                .WR_DATA_19(w_mux_19.WR_DATA),
                .WR_SRAM_NUM_19(w_mux_19.WR_SRAM_NUM),
                .WR_EN_20(w_mux_20.WR_EN),
                .WR_ADDR_20(w_mux_20.WR_ADDR),
                .WR_DATA_20(w_mux_20.WR_DATA),
                .WR_SRAM_NUM_20(w_mux_20.WR_SRAM_NUM),
                .WR_EN_21(w_mux_21.WR_EN),
                .WR_ADDR_21(w_mux_21.WR_ADDR),
                .WR_DATA_21(w_mux_21.WR_DATA),
                .WR_SRAM_NUM_21(w_mux_21.WR_SRAM_NUM),
                .WR_EN_22(w_mux_22.WR_EN),
                .WR_ADDR_22(w_mux_22.WR_ADDR),
                .WR_DATA_22(w_mux_22.WR_DATA),
                .WR_SRAM_NUM_22(w_mux_22.WR_SRAM_NUM),
                .WR_EN_23(w_mux_23.WR_EN),
                .WR_ADDR_23(w_mux_23.WR_ADDR),
                .WR_DATA_23(w_mux_23.WR_DATA),
                .WR_SRAM_NUM_23(w_mux_23.WR_SRAM_NUM),
                .WR_EN_24(w_mux_24.WR_EN),
                .WR_ADDR_24(w_mux_24.WR_ADDR),
                .WR_DATA_24(w_mux_24.WR_DATA),
                .WR_SRAM_NUM_24(w_mux_24.WR_SRAM_NUM),
                .WR_EN_25(w_mux_25.WR_EN),
                .WR_ADDR_25(w_mux_25.WR_ADDR),
                .WR_DATA_25(w_mux_25.WR_DATA),
                .WR_SRAM_NUM_25(w_mux_25.WR_SRAM_NUM),
                .WR_EN_26(w_mux_26.WR_EN),
                .WR_ADDR_26(w_mux_26.WR_ADDR),
                .WR_DATA_26(w_mux_26.WR_DATA),
                .WR_SRAM_NUM_26(w_mux_26.WR_SRAM_NUM),
                .WR_EN_27(w_mux_27.WR_EN),
                .WR_ADDR_27(w_mux_27.WR_ADDR),
                .WR_DATA_27(w_mux_27.WR_DATA),
                .WR_SRAM_NUM_27(w_mux_27.WR_SRAM_NUM),
                .WR_EN_28(w_mux_28.WR_EN),
                .WR_ADDR_28(w_mux_28.WR_ADDR),
                .WR_DATA_28(w_mux_28.WR_DATA),
                .WR_SRAM_NUM_28(w_mux_28.WR_SRAM_NUM),
                .WR_EN_29(w_mux_29.WR_EN),
                .WR_ADDR_29(w_mux_29.WR_ADDR),
                .WR_DATA_29(w_mux_29.WR_DATA),
                .WR_SRAM_NUM_29(w_mux_29.WR_SRAM_NUM),
                .WR_EN_30(w_mux_30.WR_EN),
                .WR_ADDR_30(w_mux_30.WR_ADDR),
                .WR_DATA_30(w_mux_30.WR_DATA),
                .WR_SRAM_NUM_30(w_mux_30.WR_SRAM_NUM),
                .WR_EN_31(w_mux_31.WR_EN),
                .WR_ADDR_31(w_mux_31.WR_ADDR),
                .WR_DATA_31(w_mux_31.WR_DATA),
                .WR_SRAM_NUM_31(w_mux_31.WR_SRAM_NUM),
                .WR_EN_32(w_mux_32.WR_EN),
                .WR_ADDR_32(w_mux_32.WR_ADDR),
                .WR_DATA_32(w_mux_32.WR_DATA),
                .WR_SRAM_NUM_32(w_mux_32.WR_SRAM_NUM),
                .WR_EN_33(w_mux_33.WR_EN),
                .WR_ADDR_33(w_mux_33.WR_ADDR),
                .WR_DATA_33(w_mux_33.WR_DATA),
                .WR_SRAM_NUM_33(w_mux_33.WR_SRAM_NUM),
                .WR_EN_34(w_mux_34.WR_EN),
                .WR_ADDR_34(w_mux_34.WR_ADDR),
                .WR_DATA_34(w_mux_34.WR_DATA),
                .WR_SRAM_NUM_34(w_mux_34.WR_SRAM_NUM),
                .WR_EN_35(w_mux_35.WR_EN),
                .WR_ADDR_35(w_mux_35.WR_ADDR),
                .WR_DATA_35(w_mux_35.WR_DATA),
                .WR_SRAM_NUM_35(w_mux_35.WR_SRAM_NUM),
                .WR_EN_36(w_mux_36.WR_EN),
                .WR_ADDR_36(w_mux_36.WR_ADDR),
                .WR_DATA_36(w_mux_36.WR_DATA),
                .WR_SRAM_NUM_36(w_mux_36.WR_SRAM_NUM),
                .WR_EN_37(w_mux_37.WR_EN),
                .WR_ADDR_37(w_mux_37.WR_ADDR),
                .WR_DATA_37(w_mux_37.WR_DATA),
                .WR_SRAM_NUM_37(w_mux_37.WR_SRAM_NUM),
                .WR_EN_38(w_mux_38.WR_EN),
                .WR_ADDR_38(w_mux_38.WR_ADDR),
                .WR_DATA_38(w_mux_38.WR_DATA),
                .WR_SRAM_NUM_38(w_mux_38.WR_SRAM_NUM),
                .WR_EN_39(w_mux_39.WR_EN),
                .WR_ADDR_39(w_mux_39.WR_ADDR),
                .WR_DATA_39(w_mux_39.WR_DATA),
                .WR_SRAM_NUM_39(w_mux_39.WR_SRAM_NUM),
                .WR_EN_40(w_mux_40.WR_EN),
                .WR_ADDR_40(w_mux_40.WR_ADDR),
                .WR_DATA_40(w_mux_40.WR_DATA),
                .WR_SRAM_NUM_40(w_mux_40.WR_SRAM_NUM),
                .WR_EN_41(w_mux_41.WR_EN),
                .WR_ADDR_41(w_mux_41.WR_ADDR),
                .WR_DATA_41(w_mux_41.WR_DATA),
                .WR_SRAM_NUM_41(w_mux_41.WR_SRAM_NUM),
                .WR_EN_42(w_mux_42.WR_EN),
                .WR_ADDR_42(w_mux_42.WR_ADDR),
                .WR_DATA_42(w_mux_42.WR_DATA),
                .WR_SRAM_NUM_42(w_mux_42.WR_SRAM_NUM),
                .WR_EN_43(w_mux_43.WR_EN),
                .WR_ADDR_43(w_mux_43.WR_ADDR),
                .WR_DATA_43(w_mux_43.WR_DATA),
                .WR_SRAM_NUM_43(w_mux_43.WR_SRAM_NUM),
                .WR_EN_44(w_mux_44.WR_EN),
                .WR_ADDR_44(w_mux_44.WR_ADDR),
                .WR_DATA_44(w_mux_44.WR_DATA),
                .WR_SRAM_NUM_44(w_mux_44.WR_SRAM_NUM),
                .WR_EN_45(w_mux_45.WR_EN),
                .WR_ADDR_45(w_mux_45.WR_ADDR),
                .WR_DATA_45(w_mux_45.WR_DATA),
                .WR_SRAM_NUM_45(w_mux_45.WR_SRAM_NUM),
                .WR_EN_46(w_mux_46.WR_EN),
                .WR_ADDR_46(w_mux_46.WR_ADDR),
                .WR_DATA_46(w_mux_46.WR_DATA),
                .WR_SRAM_NUM_46(w_mux_46.WR_SRAM_NUM),
                .WR_EN_47(w_mux_47.WR_EN),
                .WR_ADDR_47(w_mux_47.WR_ADDR),
                .WR_DATA_47(w_mux_47.WR_DATA),
                .WR_SRAM_NUM_47(w_mux_47.WR_SRAM_NUM),
                .W_DATA(sram_mux_11.W_DATA),
                .W_ADDR(sram_mux_11.W_ADDR),
                .WR(sram_mux_11.WR)
            );
            wr_sram_ctrl#(.WR_SRAM_num(28))
            sram_ctrl_u_12(
                .WR_EN_0(w_mux_0.WR_EN),
                .WR_ADDR_0(w_mux_0.WR_ADDR),
                .WR_DATA_0(w_mux_0.WR_DATA),
                .WR_SRAM_NUM_0(w_mux_0.WR_SRAM_NUM),
                .WR_EN_1(w_mux_1.WR_EN),
                .WR_ADDR_1(w_mux_1.WR_ADDR),
                .WR_DATA_1(w_mux_1.WR_DATA),
                .WR_SRAM_NUM_1(w_mux_1.WR_SRAM_NUM),
                .WR_EN_2(w_mux_2.WR_EN),
                .WR_ADDR_2(w_mux_2.WR_ADDR),
                .WR_DATA_2(w_mux_2.WR_DATA),
                .WR_SRAM_NUM_2(w_mux_2.WR_SRAM_NUM),
                .WR_EN_3(w_mux_3.WR_EN),
                .WR_ADDR_3(w_mux_3.WR_ADDR),
                .WR_DATA_3(w_mux_3.WR_DATA),
                .WR_SRAM_NUM_3(w_mux_3.WR_SRAM_NUM),
                .WR_EN_4(w_mux_4.WR_EN),
                .WR_ADDR_4(w_mux_4.WR_ADDR),
                .WR_DATA_4(w_mux_4.WR_DATA),
                .WR_SRAM_NUM_4(w_mux_4.WR_SRAM_NUM),
                .WR_EN_5(w_mux_5.WR_EN),
                .WR_ADDR_5(w_mux_5.WR_ADDR),
                .WR_DATA_5(w_mux_5.WR_DATA),
                .WR_SRAM_NUM_5(w_mux_5.WR_SRAM_NUM),
                .WR_EN_6(w_mux_6.WR_EN),
                .WR_ADDR_6(w_mux_6.WR_ADDR),
                .WR_DATA_6(w_mux_6.WR_DATA),
                .WR_SRAM_NUM_6(w_mux_6.WR_SRAM_NUM),
                .WR_EN_7(w_mux_7.WR_EN),
                .WR_ADDR_7(w_mux_7.WR_ADDR),
                .WR_DATA_7(w_mux_7.WR_DATA),
                .WR_SRAM_NUM_7(w_mux_7.WR_SRAM_NUM),
                .WR_EN_8(w_mux_8.WR_EN),
                .WR_ADDR_8(w_mux_8.WR_ADDR),
                .WR_DATA_8(w_mux_8.WR_DATA),
                .WR_SRAM_NUM_8(w_mux_8.WR_SRAM_NUM),
                .WR_EN_9(w_mux_9.WR_EN),
                .WR_ADDR_9(w_mux_9.WR_ADDR),
                .WR_DATA_9(w_mux_9.WR_DATA),
                .WR_SRAM_NUM_9(w_mux_9.WR_SRAM_NUM),
                .WR_EN_10(w_mux_10.WR_EN),
                .WR_ADDR_10(w_mux_10.WR_ADDR),
                .WR_DATA_10(w_mux_10.WR_DATA),
                .WR_SRAM_NUM_10(w_mux_10.WR_SRAM_NUM),
                .WR_EN_11(w_mux_11.WR_EN),
                .WR_ADDR_11(w_mux_11.WR_ADDR),
                .WR_DATA_11(w_mux_11.WR_DATA),
                .WR_SRAM_NUM_11(w_mux_11.WR_SRAM_NUM),
                .WR_EN_12(w_mux_12.WR_EN),
                .WR_ADDR_12(w_mux_12.WR_ADDR),
                .WR_DATA_12(w_mux_12.WR_DATA),
                .WR_SRAM_NUM_12(w_mux_12.WR_SRAM_NUM),
                .WR_EN_13(w_mux_13.WR_EN),
                .WR_ADDR_13(w_mux_13.WR_ADDR),
                .WR_DATA_13(w_mux_13.WR_DATA),
                .WR_SRAM_NUM_13(w_mux_13.WR_SRAM_NUM),
                .WR_EN_14(w_mux_14.WR_EN),
                .WR_ADDR_14(w_mux_14.WR_ADDR),
                .WR_DATA_14(w_mux_14.WR_DATA),
                .WR_SRAM_NUM_14(w_mux_14.WR_SRAM_NUM),
                .WR_EN_15(w_mux_15.WR_EN),
                .WR_ADDR_15(w_mux_15.WR_ADDR),
                .WR_DATA_15(w_mux_15.WR_DATA),
                .WR_SRAM_NUM_15(w_mux_15.WR_SRAM_NUM),
                .WR_EN_16(w_mux_16.WR_EN),
                .WR_ADDR_16(w_mux_16.WR_ADDR),
                .WR_DATA_16(w_mux_16.WR_DATA),
                .WR_SRAM_NUM_16(w_mux_16.WR_SRAM_NUM),
                .WR_EN_17(w_mux_17.WR_EN),
                .WR_ADDR_17(w_mux_17.WR_ADDR),
                .WR_DATA_17(w_mux_17.WR_DATA),
                .WR_SRAM_NUM_17(w_mux_17.WR_SRAM_NUM),
                .WR_EN_18(w_mux_18.WR_EN),
                .WR_ADDR_18(w_mux_18.WR_ADDR),
                .WR_DATA_18(w_mux_18.WR_DATA),
                .WR_SRAM_NUM_18(w_mux_18.WR_SRAM_NUM),
                .WR_EN_19(w_mux_19.WR_EN),
                .WR_ADDR_19(w_mux_19.WR_ADDR),
                .WR_DATA_19(w_mux_19.WR_DATA),
                .WR_SRAM_NUM_19(w_mux_19.WR_SRAM_NUM),
                .WR_EN_20(w_mux_20.WR_EN),
                .WR_ADDR_20(w_mux_20.WR_ADDR),
                .WR_DATA_20(w_mux_20.WR_DATA),
                .WR_SRAM_NUM_20(w_mux_20.WR_SRAM_NUM),
                .WR_EN_21(w_mux_21.WR_EN),
                .WR_ADDR_21(w_mux_21.WR_ADDR),
                .WR_DATA_21(w_mux_21.WR_DATA),
                .WR_SRAM_NUM_21(w_mux_21.WR_SRAM_NUM),
                .WR_EN_22(w_mux_22.WR_EN),
                .WR_ADDR_22(w_mux_22.WR_ADDR),
                .WR_DATA_22(w_mux_22.WR_DATA),
                .WR_SRAM_NUM_22(w_mux_22.WR_SRAM_NUM),
                .WR_EN_23(w_mux_23.WR_EN),
                .WR_ADDR_23(w_mux_23.WR_ADDR),
                .WR_DATA_23(w_mux_23.WR_DATA),
                .WR_SRAM_NUM_23(w_mux_23.WR_SRAM_NUM),
                .WR_EN_24(w_mux_24.WR_EN),
                .WR_ADDR_24(w_mux_24.WR_ADDR),
                .WR_DATA_24(w_mux_24.WR_DATA),
                .WR_SRAM_NUM_24(w_mux_24.WR_SRAM_NUM),
                .WR_EN_25(w_mux_25.WR_EN),
                .WR_ADDR_25(w_mux_25.WR_ADDR),
                .WR_DATA_25(w_mux_25.WR_DATA),
                .WR_SRAM_NUM_25(w_mux_25.WR_SRAM_NUM),
                .WR_EN_26(w_mux_26.WR_EN),
                .WR_ADDR_26(w_mux_26.WR_ADDR),
                .WR_DATA_26(w_mux_26.WR_DATA),
                .WR_SRAM_NUM_26(w_mux_26.WR_SRAM_NUM),
                .WR_EN_27(w_mux_27.WR_EN),
                .WR_ADDR_27(w_mux_27.WR_ADDR),
                .WR_DATA_27(w_mux_27.WR_DATA),
                .WR_SRAM_NUM_27(w_mux_27.WR_SRAM_NUM),
                .WR_EN_28(w_mux_28.WR_EN),
                .WR_ADDR_28(w_mux_28.WR_ADDR),
                .WR_DATA_28(w_mux_28.WR_DATA),
                .WR_SRAM_NUM_28(w_mux_28.WR_SRAM_NUM),
                .WR_EN_29(w_mux_29.WR_EN),
                .WR_ADDR_29(w_mux_29.WR_ADDR),
                .WR_DATA_29(w_mux_29.WR_DATA),
                .WR_SRAM_NUM_29(w_mux_29.WR_SRAM_NUM),
                .WR_EN_30(w_mux_30.WR_EN),
                .WR_ADDR_30(w_mux_30.WR_ADDR),
                .WR_DATA_30(w_mux_30.WR_DATA),
                .WR_SRAM_NUM_30(w_mux_30.WR_SRAM_NUM),
                .WR_EN_31(w_mux_31.WR_EN),
                .WR_ADDR_31(w_mux_31.WR_ADDR),
                .WR_DATA_31(w_mux_31.WR_DATA),
                .WR_SRAM_NUM_31(w_mux_31.WR_SRAM_NUM),
                .WR_EN_32(w_mux_32.WR_EN),
                .WR_ADDR_32(w_mux_32.WR_ADDR),
                .WR_DATA_32(w_mux_32.WR_DATA),
                .WR_SRAM_NUM_32(w_mux_32.WR_SRAM_NUM),
                .WR_EN_33(w_mux_33.WR_EN),
                .WR_ADDR_33(w_mux_33.WR_ADDR),
                .WR_DATA_33(w_mux_33.WR_DATA),
                .WR_SRAM_NUM_33(w_mux_33.WR_SRAM_NUM),
                .WR_EN_34(w_mux_34.WR_EN),
                .WR_ADDR_34(w_mux_34.WR_ADDR),
                .WR_DATA_34(w_mux_34.WR_DATA),
                .WR_SRAM_NUM_34(w_mux_34.WR_SRAM_NUM),
                .WR_EN_35(w_mux_35.WR_EN),
                .WR_ADDR_35(w_mux_35.WR_ADDR),
                .WR_DATA_35(w_mux_35.WR_DATA),
                .WR_SRAM_NUM_35(w_mux_35.WR_SRAM_NUM),
                .WR_EN_36(w_mux_36.WR_EN),
                .WR_ADDR_36(w_mux_36.WR_ADDR),
                .WR_DATA_36(w_mux_36.WR_DATA),
                .WR_SRAM_NUM_36(w_mux_36.WR_SRAM_NUM),
                .WR_EN_37(w_mux_37.WR_EN),
                .WR_ADDR_37(w_mux_37.WR_ADDR),
                .WR_DATA_37(w_mux_37.WR_DATA),
                .WR_SRAM_NUM_37(w_mux_37.WR_SRAM_NUM),
                .WR_EN_38(w_mux_38.WR_EN),
                .WR_ADDR_38(w_mux_38.WR_ADDR),
                .WR_DATA_38(w_mux_38.WR_DATA),
                .WR_SRAM_NUM_38(w_mux_38.WR_SRAM_NUM),
                .WR_EN_39(w_mux_39.WR_EN),
                .WR_ADDR_39(w_mux_39.WR_ADDR),
                .WR_DATA_39(w_mux_39.WR_DATA),
                .WR_SRAM_NUM_39(w_mux_39.WR_SRAM_NUM),
                .WR_EN_40(w_mux_40.WR_EN),
                .WR_ADDR_40(w_mux_40.WR_ADDR),
                .WR_DATA_40(w_mux_40.WR_DATA),
                .WR_SRAM_NUM_40(w_mux_40.WR_SRAM_NUM),
                .WR_EN_41(w_mux_41.WR_EN),
                .WR_ADDR_41(w_mux_41.WR_ADDR),
                .WR_DATA_41(w_mux_41.WR_DATA),
                .WR_SRAM_NUM_41(w_mux_41.WR_SRAM_NUM),
                .WR_EN_42(w_mux_42.WR_EN),
                .WR_ADDR_42(w_mux_42.WR_ADDR),
                .WR_DATA_42(w_mux_42.WR_DATA),
                .WR_SRAM_NUM_42(w_mux_42.WR_SRAM_NUM),
                .WR_EN_43(w_mux_43.WR_EN),
                .WR_ADDR_43(w_mux_43.WR_ADDR),
                .WR_DATA_43(w_mux_43.WR_DATA),
                .WR_SRAM_NUM_43(w_mux_43.WR_SRAM_NUM),
                .WR_EN_44(w_mux_44.WR_EN),
                .WR_ADDR_44(w_mux_44.WR_ADDR),
                .WR_DATA_44(w_mux_44.WR_DATA),
                .WR_SRAM_NUM_44(w_mux_44.WR_SRAM_NUM),
                .WR_EN_45(w_mux_45.WR_EN),
                .WR_ADDR_45(w_mux_45.WR_ADDR),
                .WR_DATA_45(w_mux_45.WR_DATA),
                .WR_SRAM_NUM_45(w_mux_45.WR_SRAM_NUM),
                .WR_EN_46(w_mux_46.WR_EN),
                .WR_ADDR_46(w_mux_46.WR_ADDR),
                .WR_DATA_46(w_mux_46.WR_DATA),
                .WR_SRAM_NUM_46(w_mux_46.WR_SRAM_NUM),
                .WR_EN_47(w_mux_47.WR_EN),
                .WR_ADDR_47(w_mux_47.WR_ADDR),
                .WR_DATA_47(w_mux_47.WR_DATA),
                .WR_SRAM_NUM_47(w_mux_47.WR_SRAM_NUM),
                .W_DATA(sram_mux_12.W_DATA),
                .W_ADDR(sram_mux_12.W_ADDR),
                .WR(sram_mux_12.WR)
            );
            wr_sram_ctrl#(.WR_SRAM_num(29))
            sram_ctrl_u_13(
                .WR_EN_0(w_mux_0.WR_EN),
                .WR_ADDR_0(w_mux_0.WR_ADDR),
                .WR_DATA_0(w_mux_0.WR_DATA),
                .WR_SRAM_NUM_0(w_mux_0.WR_SRAM_NUM),
                .WR_EN_1(w_mux_1.WR_EN),
                .WR_ADDR_1(w_mux_1.WR_ADDR),
                .WR_DATA_1(w_mux_1.WR_DATA),
                .WR_SRAM_NUM_1(w_mux_1.WR_SRAM_NUM),
                .WR_EN_2(w_mux_2.WR_EN),
                .WR_ADDR_2(w_mux_2.WR_ADDR),
                .WR_DATA_2(w_mux_2.WR_DATA),
                .WR_SRAM_NUM_2(w_mux_2.WR_SRAM_NUM),
                .WR_EN_3(w_mux_3.WR_EN),
                .WR_ADDR_3(w_mux_3.WR_ADDR),
                .WR_DATA_3(w_mux_3.WR_DATA),
                .WR_SRAM_NUM_3(w_mux_3.WR_SRAM_NUM),
                .WR_EN_4(w_mux_4.WR_EN),
                .WR_ADDR_4(w_mux_4.WR_ADDR),
                .WR_DATA_4(w_mux_4.WR_DATA),
                .WR_SRAM_NUM_4(w_mux_4.WR_SRAM_NUM),
                .WR_EN_5(w_mux_5.WR_EN),
                .WR_ADDR_5(w_mux_5.WR_ADDR),
                .WR_DATA_5(w_mux_5.WR_DATA),
                .WR_SRAM_NUM_5(w_mux_5.WR_SRAM_NUM),
                .WR_EN_6(w_mux_6.WR_EN),
                .WR_ADDR_6(w_mux_6.WR_ADDR),
                .WR_DATA_6(w_mux_6.WR_DATA),
                .WR_SRAM_NUM_6(w_mux_6.WR_SRAM_NUM),
                .WR_EN_7(w_mux_7.WR_EN),
                .WR_ADDR_7(w_mux_7.WR_ADDR),
                .WR_DATA_7(w_mux_7.WR_DATA),
                .WR_SRAM_NUM_7(w_mux_7.WR_SRAM_NUM),
                .WR_EN_8(w_mux_8.WR_EN),
                .WR_ADDR_8(w_mux_8.WR_ADDR),
                .WR_DATA_8(w_mux_8.WR_DATA),
                .WR_SRAM_NUM_8(w_mux_8.WR_SRAM_NUM),
                .WR_EN_9(w_mux_9.WR_EN),
                .WR_ADDR_9(w_mux_9.WR_ADDR),
                .WR_DATA_9(w_mux_9.WR_DATA),
                .WR_SRAM_NUM_9(w_mux_9.WR_SRAM_NUM),
                .WR_EN_10(w_mux_10.WR_EN),
                .WR_ADDR_10(w_mux_10.WR_ADDR),
                .WR_DATA_10(w_mux_10.WR_DATA),
                .WR_SRAM_NUM_10(w_mux_10.WR_SRAM_NUM),
                .WR_EN_11(w_mux_11.WR_EN),
                .WR_ADDR_11(w_mux_11.WR_ADDR),
                .WR_DATA_11(w_mux_11.WR_DATA),
                .WR_SRAM_NUM_11(w_mux_11.WR_SRAM_NUM),
                .WR_EN_12(w_mux_12.WR_EN),
                .WR_ADDR_12(w_mux_12.WR_ADDR),
                .WR_DATA_12(w_mux_12.WR_DATA),
                .WR_SRAM_NUM_12(w_mux_12.WR_SRAM_NUM),
                .WR_EN_13(w_mux_13.WR_EN),
                .WR_ADDR_13(w_mux_13.WR_ADDR),
                .WR_DATA_13(w_mux_13.WR_DATA),
                .WR_SRAM_NUM_13(w_mux_13.WR_SRAM_NUM),
                .WR_EN_14(w_mux_14.WR_EN),
                .WR_ADDR_14(w_mux_14.WR_ADDR),
                .WR_DATA_14(w_mux_14.WR_DATA),
                .WR_SRAM_NUM_14(w_mux_14.WR_SRAM_NUM),
                .WR_EN_15(w_mux_15.WR_EN),
                .WR_ADDR_15(w_mux_15.WR_ADDR),
                .WR_DATA_15(w_mux_15.WR_DATA),
                .WR_SRAM_NUM_15(w_mux_15.WR_SRAM_NUM),
                .WR_EN_16(w_mux_16.WR_EN),
                .WR_ADDR_16(w_mux_16.WR_ADDR),
                .WR_DATA_16(w_mux_16.WR_DATA),
                .WR_SRAM_NUM_16(w_mux_16.WR_SRAM_NUM),
                .WR_EN_17(w_mux_17.WR_EN),
                .WR_ADDR_17(w_mux_17.WR_ADDR),
                .WR_DATA_17(w_mux_17.WR_DATA),
                .WR_SRAM_NUM_17(w_mux_17.WR_SRAM_NUM),
                .WR_EN_18(w_mux_18.WR_EN),
                .WR_ADDR_18(w_mux_18.WR_ADDR),
                .WR_DATA_18(w_mux_18.WR_DATA),
                .WR_SRAM_NUM_18(w_mux_18.WR_SRAM_NUM),
                .WR_EN_19(w_mux_19.WR_EN),
                .WR_ADDR_19(w_mux_19.WR_ADDR),
                .WR_DATA_19(w_mux_19.WR_DATA),
                .WR_SRAM_NUM_19(w_mux_19.WR_SRAM_NUM),
                .WR_EN_20(w_mux_20.WR_EN),
                .WR_ADDR_20(w_mux_20.WR_ADDR),
                .WR_DATA_20(w_mux_20.WR_DATA),
                .WR_SRAM_NUM_20(w_mux_20.WR_SRAM_NUM),
                .WR_EN_21(w_mux_21.WR_EN),
                .WR_ADDR_21(w_mux_21.WR_ADDR),
                .WR_DATA_21(w_mux_21.WR_DATA),
                .WR_SRAM_NUM_21(w_mux_21.WR_SRAM_NUM),
                .WR_EN_22(w_mux_22.WR_EN),
                .WR_ADDR_22(w_mux_22.WR_ADDR),
                .WR_DATA_22(w_mux_22.WR_DATA),
                .WR_SRAM_NUM_22(w_mux_22.WR_SRAM_NUM),
                .WR_EN_23(w_mux_23.WR_EN),
                .WR_ADDR_23(w_mux_23.WR_ADDR),
                .WR_DATA_23(w_mux_23.WR_DATA),
                .WR_SRAM_NUM_23(w_mux_23.WR_SRAM_NUM),
                .WR_EN_24(w_mux_24.WR_EN),
                .WR_ADDR_24(w_mux_24.WR_ADDR),
                .WR_DATA_24(w_mux_24.WR_DATA),
                .WR_SRAM_NUM_24(w_mux_24.WR_SRAM_NUM),
                .WR_EN_25(w_mux_25.WR_EN),
                .WR_ADDR_25(w_mux_25.WR_ADDR),
                .WR_DATA_25(w_mux_25.WR_DATA),
                .WR_SRAM_NUM_25(w_mux_25.WR_SRAM_NUM),
                .WR_EN_26(w_mux_26.WR_EN),
                .WR_ADDR_26(w_mux_26.WR_ADDR),
                .WR_DATA_26(w_mux_26.WR_DATA),
                .WR_SRAM_NUM_26(w_mux_26.WR_SRAM_NUM),
                .WR_EN_27(w_mux_27.WR_EN),
                .WR_ADDR_27(w_mux_27.WR_ADDR),
                .WR_DATA_27(w_mux_27.WR_DATA),
                .WR_SRAM_NUM_27(w_mux_27.WR_SRAM_NUM),
                .WR_EN_28(w_mux_28.WR_EN),
                .WR_ADDR_28(w_mux_28.WR_ADDR),
                .WR_DATA_28(w_mux_28.WR_DATA),
                .WR_SRAM_NUM_28(w_mux_28.WR_SRAM_NUM),
                .WR_EN_29(w_mux_29.WR_EN),
                .WR_ADDR_29(w_mux_29.WR_ADDR),
                .WR_DATA_29(w_mux_29.WR_DATA),
                .WR_SRAM_NUM_29(w_mux_29.WR_SRAM_NUM),
                .WR_EN_30(w_mux_30.WR_EN),
                .WR_ADDR_30(w_mux_30.WR_ADDR),
                .WR_DATA_30(w_mux_30.WR_DATA),
                .WR_SRAM_NUM_30(w_mux_30.WR_SRAM_NUM),
                .WR_EN_31(w_mux_31.WR_EN),
                .WR_ADDR_31(w_mux_31.WR_ADDR),
                .WR_DATA_31(w_mux_31.WR_DATA),
                .WR_SRAM_NUM_31(w_mux_31.WR_SRAM_NUM),
                .WR_EN_32(w_mux_32.WR_EN),
                .WR_ADDR_32(w_mux_32.WR_ADDR),
                .WR_DATA_32(w_mux_32.WR_DATA),
                .WR_SRAM_NUM_32(w_mux_32.WR_SRAM_NUM),
                .WR_EN_33(w_mux_33.WR_EN),
                .WR_ADDR_33(w_mux_33.WR_ADDR),
                .WR_DATA_33(w_mux_33.WR_DATA),
                .WR_SRAM_NUM_33(w_mux_33.WR_SRAM_NUM),
                .WR_EN_34(w_mux_34.WR_EN),
                .WR_ADDR_34(w_mux_34.WR_ADDR),
                .WR_DATA_34(w_mux_34.WR_DATA),
                .WR_SRAM_NUM_34(w_mux_34.WR_SRAM_NUM),
                .WR_EN_35(w_mux_35.WR_EN),
                .WR_ADDR_35(w_mux_35.WR_ADDR),
                .WR_DATA_35(w_mux_35.WR_DATA),
                .WR_SRAM_NUM_35(w_mux_35.WR_SRAM_NUM),
                .WR_EN_36(w_mux_36.WR_EN),
                .WR_ADDR_36(w_mux_36.WR_ADDR),
                .WR_DATA_36(w_mux_36.WR_DATA),
                .WR_SRAM_NUM_36(w_mux_36.WR_SRAM_NUM),
                .WR_EN_37(w_mux_37.WR_EN),
                .WR_ADDR_37(w_mux_37.WR_ADDR),
                .WR_DATA_37(w_mux_37.WR_DATA),
                .WR_SRAM_NUM_37(w_mux_37.WR_SRAM_NUM),
                .WR_EN_38(w_mux_38.WR_EN),
                .WR_ADDR_38(w_mux_38.WR_ADDR),
                .WR_DATA_38(w_mux_38.WR_DATA),
                .WR_SRAM_NUM_38(w_mux_38.WR_SRAM_NUM),
                .WR_EN_39(w_mux_39.WR_EN),
                .WR_ADDR_39(w_mux_39.WR_ADDR),
                .WR_DATA_39(w_mux_39.WR_DATA),
                .WR_SRAM_NUM_39(w_mux_39.WR_SRAM_NUM),
                .WR_EN_40(w_mux_40.WR_EN),
                .WR_ADDR_40(w_mux_40.WR_ADDR),
                .WR_DATA_40(w_mux_40.WR_DATA),
                .WR_SRAM_NUM_40(w_mux_40.WR_SRAM_NUM),
                .WR_EN_41(w_mux_41.WR_EN),
                .WR_ADDR_41(w_mux_41.WR_ADDR),
                .WR_DATA_41(w_mux_41.WR_DATA),
                .WR_SRAM_NUM_41(w_mux_41.WR_SRAM_NUM),
                .WR_EN_42(w_mux_42.WR_EN),
                .WR_ADDR_42(w_mux_42.WR_ADDR),
                .WR_DATA_42(w_mux_42.WR_DATA),
                .WR_SRAM_NUM_42(w_mux_42.WR_SRAM_NUM),
                .WR_EN_43(w_mux_43.WR_EN),
                .WR_ADDR_43(w_mux_43.WR_ADDR),
                .WR_DATA_43(w_mux_43.WR_DATA),
                .WR_SRAM_NUM_43(w_mux_43.WR_SRAM_NUM),
                .WR_EN_44(w_mux_44.WR_EN),
                .WR_ADDR_44(w_mux_44.WR_ADDR),
                .WR_DATA_44(w_mux_44.WR_DATA),
                .WR_SRAM_NUM_44(w_mux_44.WR_SRAM_NUM),
                .WR_EN_45(w_mux_45.WR_EN),
                .WR_ADDR_45(w_mux_45.WR_ADDR),
                .WR_DATA_45(w_mux_45.WR_DATA),
                .WR_SRAM_NUM_45(w_mux_45.WR_SRAM_NUM),
                .WR_EN_46(w_mux_46.WR_EN),
                .WR_ADDR_46(w_mux_46.WR_ADDR),
                .WR_DATA_46(w_mux_46.WR_DATA),
                .WR_SRAM_NUM_46(w_mux_46.WR_SRAM_NUM),
                .WR_EN_47(w_mux_47.WR_EN),
                .WR_ADDR_47(w_mux_47.WR_ADDR),
                .WR_DATA_47(w_mux_47.WR_DATA),
                .WR_SRAM_NUM_47(w_mux_47.WR_SRAM_NUM),
                .W_DATA(sram_mux_13.W_DATA),
                .W_ADDR(sram_mux_13.W_ADDR),
                .WR(sram_mux_13.WR)
            );
            wr_sram_ctrl#(.WR_SRAM_num(30))
            sram_ctrl_u_14(
                .WR_EN_0(w_mux_0.WR_EN),
                .WR_ADDR_0(w_mux_0.WR_ADDR),
                .WR_DATA_0(w_mux_0.WR_DATA),
                .WR_SRAM_NUM_0(w_mux_0.WR_SRAM_NUM),
                .WR_EN_1(w_mux_1.WR_EN),
                .WR_ADDR_1(w_mux_1.WR_ADDR),
                .WR_DATA_1(w_mux_1.WR_DATA),
                .WR_SRAM_NUM_1(w_mux_1.WR_SRAM_NUM),
                .WR_EN_2(w_mux_2.WR_EN),
                .WR_ADDR_2(w_mux_2.WR_ADDR),
                .WR_DATA_2(w_mux_2.WR_DATA),
                .WR_SRAM_NUM_2(w_mux_2.WR_SRAM_NUM),
                .WR_EN_3(w_mux_3.WR_EN),
                .WR_ADDR_3(w_mux_3.WR_ADDR),
                .WR_DATA_3(w_mux_3.WR_DATA),
                .WR_SRAM_NUM_3(w_mux_3.WR_SRAM_NUM),
                .WR_EN_4(w_mux_4.WR_EN),
                .WR_ADDR_4(w_mux_4.WR_ADDR),
                .WR_DATA_4(w_mux_4.WR_DATA),
                .WR_SRAM_NUM_4(w_mux_4.WR_SRAM_NUM),
                .WR_EN_5(w_mux_5.WR_EN),
                .WR_ADDR_5(w_mux_5.WR_ADDR),
                .WR_DATA_5(w_mux_5.WR_DATA),
                .WR_SRAM_NUM_5(w_mux_5.WR_SRAM_NUM),
                .WR_EN_6(w_mux_6.WR_EN),
                .WR_ADDR_6(w_mux_6.WR_ADDR),
                .WR_DATA_6(w_mux_6.WR_DATA),
                .WR_SRAM_NUM_6(w_mux_6.WR_SRAM_NUM),
                .WR_EN_7(w_mux_7.WR_EN),
                .WR_ADDR_7(w_mux_7.WR_ADDR),
                .WR_DATA_7(w_mux_7.WR_DATA),
                .WR_SRAM_NUM_7(w_mux_7.WR_SRAM_NUM),
                .WR_EN_8(w_mux_8.WR_EN),
                .WR_ADDR_8(w_mux_8.WR_ADDR),
                .WR_DATA_8(w_mux_8.WR_DATA),
                .WR_SRAM_NUM_8(w_mux_8.WR_SRAM_NUM),
                .WR_EN_9(w_mux_9.WR_EN),
                .WR_ADDR_9(w_mux_9.WR_ADDR),
                .WR_DATA_9(w_mux_9.WR_DATA),
                .WR_SRAM_NUM_9(w_mux_9.WR_SRAM_NUM),
                .WR_EN_10(w_mux_10.WR_EN),
                .WR_ADDR_10(w_mux_10.WR_ADDR),
                .WR_DATA_10(w_mux_10.WR_DATA),
                .WR_SRAM_NUM_10(w_mux_10.WR_SRAM_NUM),
                .WR_EN_11(w_mux_11.WR_EN),
                .WR_ADDR_11(w_mux_11.WR_ADDR),
                .WR_DATA_11(w_mux_11.WR_DATA),
                .WR_SRAM_NUM_11(w_mux_11.WR_SRAM_NUM),
                .WR_EN_12(w_mux_12.WR_EN),
                .WR_ADDR_12(w_mux_12.WR_ADDR),
                .WR_DATA_12(w_mux_12.WR_DATA),
                .WR_SRAM_NUM_12(w_mux_12.WR_SRAM_NUM),
                .WR_EN_13(w_mux_13.WR_EN),
                .WR_ADDR_13(w_mux_13.WR_ADDR),
                .WR_DATA_13(w_mux_13.WR_DATA),
                .WR_SRAM_NUM_13(w_mux_13.WR_SRAM_NUM),
                .WR_EN_14(w_mux_14.WR_EN),
                .WR_ADDR_14(w_mux_14.WR_ADDR),
                .WR_DATA_14(w_mux_14.WR_DATA),
                .WR_SRAM_NUM_14(w_mux_14.WR_SRAM_NUM),
                .WR_EN_15(w_mux_15.WR_EN),
                .WR_ADDR_15(w_mux_15.WR_ADDR),
                .WR_DATA_15(w_mux_15.WR_DATA),
                .WR_SRAM_NUM_15(w_mux_15.WR_SRAM_NUM),
                .WR_EN_16(w_mux_16.WR_EN),
                .WR_ADDR_16(w_mux_16.WR_ADDR),
                .WR_DATA_16(w_mux_16.WR_DATA),
                .WR_SRAM_NUM_16(w_mux_16.WR_SRAM_NUM),
                .WR_EN_17(w_mux_17.WR_EN),
                .WR_ADDR_17(w_mux_17.WR_ADDR),
                .WR_DATA_17(w_mux_17.WR_DATA),
                .WR_SRAM_NUM_17(w_mux_17.WR_SRAM_NUM),
                .WR_EN_18(w_mux_18.WR_EN),
                .WR_ADDR_18(w_mux_18.WR_ADDR),
                .WR_DATA_18(w_mux_18.WR_DATA),
                .WR_SRAM_NUM_18(w_mux_18.WR_SRAM_NUM),
                .WR_EN_19(w_mux_19.WR_EN),
                .WR_ADDR_19(w_mux_19.WR_ADDR),
                .WR_DATA_19(w_mux_19.WR_DATA),
                .WR_SRAM_NUM_19(w_mux_19.WR_SRAM_NUM),
                .WR_EN_20(w_mux_20.WR_EN),
                .WR_ADDR_20(w_mux_20.WR_ADDR),
                .WR_DATA_20(w_mux_20.WR_DATA),
                .WR_SRAM_NUM_20(w_mux_20.WR_SRAM_NUM),
                .WR_EN_21(w_mux_21.WR_EN),
                .WR_ADDR_21(w_mux_21.WR_ADDR),
                .WR_DATA_21(w_mux_21.WR_DATA),
                .WR_SRAM_NUM_21(w_mux_21.WR_SRAM_NUM),
                .WR_EN_22(w_mux_22.WR_EN),
                .WR_ADDR_22(w_mux_22.WR_ADDR),
                .WR_DATA_22(w_mux_22.WR_DATA),
                .WR_SRAM_NUM_22(w_mux_22.WR_SRAM_NUM),
                .WR_EN_23(w_mux_23.WR_EN),
                .WR_ADDR_23(w_mux_23.WR_ADDR),
                .WR_DATA_23(w_mux_23.WR_DATA),
                .WR_SRAM_NUM_23(w_mux_23.WR_SRAM_NUM),
                .WR_EN_24(w_mux_24.WR_EN),
                .WR_ADDR_24(w_mux_24.WR_ADDR),
                .WR_DATA_24(w_mux_24.WR_DATA),
                .WR_SRAM_NUM_24(w_mux_24.WR_SRAM_NUM),
                .WR_EN_25(w_mux_25.WR_EN),
                .WR_ADDR_25(w_mux_25.WR_ADDR),
                .WR_DATA_25(w_mux_25.WR_DATA),
                .WR_SRAM_NUM_25(w_mux_25.WR_SRAM_NUM),
                .WR_EN_26(w_mux_26.WR_EN),
                .WR_ADDR_26(w_mux_26.WR_ADDR),
                .WR_DATA_26(w_mux_26.WR_DATA),
                .WR_SRAM_NUM_26(w_mux_26.WR_SRAM_NUM),
                .WR_EN_27(w_mux_27.WR_EN),
                .WR_ADDR_27(w_mux_27.WR_ADDR),
                .WR_DATA_27(w_mux_27.WR_DATA),
                .WR_SRAM_NUM_27(w_mux_27.WR_SRAM_NUM),
                .WR_EN_28(w_mux_28.WR_EN),
                .WR_ADDR_28(w_mux_28.WR_ADDR),
                .WR_DATA_28(w_mux_28.WR_DATA),
                .WR_SRAM_NUM_28(w_mux_28.WR_SRAM_NUM),
                .WR_EN_29(w_mux_29.WR_EN),
                .WR_ADDR_29(w_mux_29.WR_ADDR),
                .WR_DATA_29(w_mux_29.WR_DATA),
                .WR_SRAM_NUM_29(w_mux_29.WR_SRAM_NUM),
                .WR_EN_30(w_mux_30.WR_EN),
                .WR_ADDR_30(w_mux_30.WR_ADDR),
                .WR_DATA_30(w_mux_30.WR_DATA),
                .WR_SRAM_NUM_30(w_mux_30.WR_SRAM_NUM),
                .WR_EN_31(w_mux_31.WR_EN),
                .WR_ADDR_31(w_mux_31.WR_ADDR),
                .WR_DATA_31(w_mux_31.WR_DATA),
                .WR_SRAM_NUM_31(w_mux_31.WR_SRAM_NUM),
                .WR_EN_32(w_mux_32.WR_EN),
                .WR_ADDR_32(w_mux_32.WR_ADDR),
                .WR_DATA_32(w_mux_32.WR_DATA),
                .WR_SRAM_NUM_32(w_mux_32.WR_SRAM_NUM),
                .WR_EN_33(w_mux_33.WR_EN),
                .WR_ADDR_33(w_mux_33.WR_ADDR),
                .WR_DATA_33(w_mux_33.WR_DATA),
                .WR_SRAM_NUM_33(w_mux_33.WR_SRAM_NUM),
                .WR_EN_34(w_mux_34.WR_EN),
                .WR_ADDR_34(w_mux_34.WR_ADDR),
                .WR_DATA_34(w_mux_34.WR_DATA),
                .WR_SRAM_NUM_34(w_mux_34.WR_SRAM_NUM),
                .WR_EN_35(w_mux_35.WR_EN),
                .WR_ADDR_35(w_mux_35.WR_ADDR),
                .WR_DATA_35(w_mux_35.WR_DATA),
                .WR_SRAM_NUM_35(w_mux_35.WR_SRAM_NUM),
                .WR_EN_36(w_mux_36.WR_EN),
                .WR_ADDR_36(w_mux_36.WR_ADDR),
                .WR_DATA_36(w_mux_36.WR_DATA),
                .WR_SRAM_NUM_36(w_mux_36.WR_SRAM_NUM),
                .WR_EN_37(w_mux_37.WR_EN),
                .WR_ADDR_37(w_mux_37.WR_ADDR),
                .WR_DATA_37(w_mux_37.WR_DATA),
                .WR_SRAM_NUM_37(w_mux_37.WR_SRAM_NUM),
                .WR_EN_38(w_mux_38.WR_EN),
                .WR_ADDR_38(w_mux_38.WR_ADDR),
                .WR_DATA_38(w_mux_38.WR_DATA),
                .WR_SRAM_NUM_38(w_mux_38.WR_SRAM_NUM),
                .WR_EN_39(w_mux_39.WR_EN),
                .WR_ADDR_39(w_mux_39.WR_ADDR),
                .WR_DATA_39(w_mux_39.WR_DATA),
                .WR_SRAM_NUM_39(w_mux_39.WR_SRAM_NUM),
                .WR_EN_40(w_mux_40.WR_EN),
                .WR_ADDR_40(w_mux_40.WR_ADDR),
                .WR_DATA_40(w_mux_40.WR_DATA),
                .WR_SRAM_NUM_40(w_mux_40.WR_SRAM_NUM),
                .WR_EN_41(w_mux_41.WR_EN),
                .WR_ADDR_41(w_mux_41.WR_ADDR),
                .WR_DATA_41(w_mux_41.WR_DATA),
                .WR_SRAM_NUM_41(w_mux_41.WR_SRAM_NUM),
                .WR_EN_42(w_mux_42.WR_EN),
                .WR_ADDR_42(w_mux_42.WR_ADDR),
                .WR_DATA_42(w_mux_42.WR_DATA),
                .WR_SRAM_NUM_42(w_mux_42.WR_SRAM_NUM),
                .WR_EN_43(w_mux_43.WR_EN),
                .WR_ADDR_43(w_mux_43.WR_ADDR),
                .WR_DATA_43(w_mux_43.WR_DATA),
                .WR_SRAM_NUM_43(w_mux_43.WR_SRAM_NUM),
                .WR_EN_44(w_mux_44.WR_EN),
                .WR_ADDR_44(w_mux_44.WR_ADDR),
                .WR_DATA_44(w_mux_44.WR_DATA),
                .WR_SRAM_NUM_44(w_mux_44.WR_SRAM_NUM),
                .WR_EN_45(w_mux_45.WR_EN),
                .WR_ADDR_45(w_mux_45.WR_ADDR),
                .WR_DATA_45(w_mux_45.WR_DATA),
                .WR_SRAM_NUM_45(w_mux_45.WR_SRAM_NUM),
                .WR_EN_46(w_mux_46.WR_EN),
                .WR_ADDR_46(w_mux_46.WR_ADDR),
                .WR_DATA_46(w_mux_46.WR_DATA),
                .WR_SRAM_NUM_46(w_mux_46.WR_SRAM_NUM),
                .WR_EN_47(w_mux_47.WR_EN),
                .WR_ADDR_47(w_mux_47.WR_ADDR),
                .WR_DATA_47(w_mux_47.WR_DATA),
                .WR_SRAM_NUM_47(w_mux_47.WR_SRAM_NUM),
                .W_DATA(sram_mux_14.W_DATA),
                .W_ADDR(sram_mux_14.W_ADDR),
                .WR(sram_mux_14.WR)
            );
            wr_sram_ctrl#(.WR_SRAM_num(31))
            sram_ctrl_u_15(
                .WR_EN_0(w_mux_0.WR_EN),
                .WR_ADDR_0(w_mux_0.WR_ADDR),
                .WR_DATA_0(w_mux_0.WR_DATA),
                .WR_SRAM_NUM_0(w_mux_0.WR_SRAM_NUM),
                .WR_EN_1(w_mux_1.WR_EN),
                .WR_ADDR_1(w_mux_1.WR_ADDR),
                .WR_DATA_1(w_mux_1.WR_DATA),
                .WR_SRAM_NUM_1(w_mux_1.WR_SRAM_NUM),
                .WR_EN_2(w_mux_2.WR_EN),
                .WR_ADDR_2(w_mux_2.WR_ADDR),
                .WR_DATA_2(w_mux_2.WR_DATA),
                .WR_SRAM_NUM_2(w_mux_2.WR_SRAM_NUM),
                .WR_EN_3(w_mux_3.WR_EN),
                .WR_ADDR_3(w_mux_3.WR_ADDR),
                .WR_DATA_3(w_mux_3.WR_DATA),
                .WR_SRAM_NUM_3(w_mux_3.WR_SRAM_NUM),
                .WR_EN_4(w_mux_4.WR_EN),
                .WR_ADDR_4(w_mux_4.WR_ADDR),
                .WR_DATA_4(w_mux_4.WR_DATA),
                .WR_SRAM_NUM_4(w_mux_4.WR_SRAM_NUM),
                .WR_EN_5(w_mux_5.WR_EN),
                .WR_ADDR_5(w_mux_5.WR_ADDR),
                .WR_DATA_5(w_mux_5.WR_DATA),
                .WR_SRAM_NUM_5(w_mux_5.WR_SRAM_NUM),
                .WR_EN_6(w_mux_6.WR_EN),
                .WR_ADDR_6(w_mux_6.WR_ADDR),
                .WR_DATA_6(w_mux_6.WR_DATA),
                .WR_SRAM_NUM_6(w_mux_6.WR_SRAM_NUM),
                .WR_EN_7(w_mux_7.WR_EN),
                .WR_ADDR_7(w_mux_7.WR_ADDR),
                .WR_DATA_7(w_mux_7.WR_DATA),
                .WR_SRAM_NUM_7(w_mux_7.WR_SRAM_NUM),
                .WR_EN_8(w_mux_8.WR_EN),
                .WR_ADDR_8(w_mux_8.WR_ADDR),
                .WR_DATA_8(w_mux_8.WR_DATA),
                .WR_SRAM_NUM_8(w_mux_8.WR_SRAM_NUM),
                .WR_EN_9(w_mux_9.WR_EN),
                .WR_ADDR_9(w_mux_9.WR_ADDR),
                .WR_DATA_9(w_mux_9.WR_DATA),
                .WR_SRAM_NUM_9(w_mux_9.WR_SRAM_NUM),
                .WR_EN_10(w_mux_10.WR_EN),
                .WR_ADDR_10(w_mux_10.WR_ADDR),
                .WR_DATA_10(w_mux_10.WR_DATA),
                .WR_SRAM_NUM_10(w_mux_10.WR_SRAM_NUM),
                .WR_EN_11(w_mux_11.WR_EN),
                .WR_ADDR_11(w_mux_11.WR_ADDR),
                .WR_DATA_11(w_mux_11.WR_DATA),
                .WR_SRAM_NUM_11(w_mux_11.WR_SRAM_NUM),
                .WR_EN_12(w_mux_12.WR_EN),
                .WR_ADDR_12(w_mux_12.WR_ADDR),
                .WR_DATA_12(w_mux_12.WR_DATA),
                .WR_SRAM_NUM_12(w_mux_12.WR_SRAM_NUM),
                .WR_EN_13(w_mux_13.WR_EN),
                .WR_ADDR_13(w_mux_13.WR_ADDR),
                .WR_DATA_13(w_mux_13.WR_DATA),
                .WR_SRAM_NUM_13(w_mux_13.WR_SRAM_NUM),
                .WR_EN_14(w_mux_14.WR_EN),
                .WR_ADDR_14(w_mux_14.WR_ADDR),
                .WR_DATA_14(w_mux_14.WR_DATA),
                .WR_SRAM_NUM_14(w_mux_14.WR_SRAM_NUM),
                .WR_EN_15(w_mux_15.WR_EN),
                .WR_ADDR_15(w_mux_15.WR_ADDR),
                .WR_DATA_15(w_mux_15.WR_DATA),
                .WR_SRAM_NUM_15(w_mux_15.WR_SRAM_NUM),
                .WR_EN_16(w_mux_16.WR_EN),
                .WR_ADDR_16(w_mux_16.WR_ADDR),
                .WR_DATA_16(w_mux_16.WR_DATA),
                .WR_SRAM_NUM_16(w_mux_16.WR_SRAM_NUM),
                .WR_EN_17(w_mux_17.WR_EN),
                .WR_ADDR_17(w_mux_17.WR_ADDR),
                .WR_DATA_17(w_mux_17.WR_DATA),
                .WR_SRAM_NUM_17(w_mux_17.WR_SRAM_NUM),
                .WR_EN_18(w_mux_18.WR_EN),
                .WR_ADDR_18(w_mux_18.WR_ADDR),
                .WR_DATA_18(w_mux_18.WR_DATA),
                .WR_SRAM_NUM_18(w_mux_18.WR_SRAM_NUM),
                .WR_EN_19(w_mux_19.WR_EN),
                .WR_ADDR_19(w_mux_19.WR_ADDR),
                .WR_DATA_19(w_mux_19.WR_DATA),
                .WR_SRAM_NUM_19(w_mux_19.WR_SRAM_NUM),
                .WR_EN_20(w_mux_20.WR_EN),
                .WR_ADDR_20(w_mux_20.WR_ADDR),
                .WR_DATA_20(w_mux_20.WR_DATA),
                .WR_SRAM_NUM_20(w_mux_20.WR_SRAM_NUM),
                .WR_EN_21(w_mux_21.WR_EN),
                .WR_ADDR_21(w_mux_21.WR_ADDR),
                .WR_DATA_21(w_mux_21.WR_DATA),
                .WR_SRAM_NUM_21(w_mux_21.WR_SRAM_NUM),
                .WR_EN_22(w_mux_22.WR_EN),
                .WR_ADDR_22(w_mux_22.WR_ADDR),
                .WR_DATA_22(w_mux_22.WR_DATA),
                .WR_SRAM_NUM_22(w_mux_22.WR_SRAM_NUM),
                .WR_EN_23(w_mux_23.WR_EN),
                .WR_ADDR_23(w_mux_23.WR_ADDR),
                .WR_DATA_23(w_mux_23.WR_DATA),
                .WR_SRAM_NUM_23(w_mux_23.WR_SRAM_NUM),
                .WR_EN_24(w_mux_24.WR_EN),
                .WR_ADDR_24(w_mux_24.WR_ADDR),
                .WR_DATA_24(w_mux_24.WR_DATA),
                .WR_SRAM_NUM_24(w_mux_24.WR_SRAM_NUM),
                .WR_EN_25(w_mux_25.WR_EN),
                .WR_ADDR_25(w_mux_25.WR_ADDR),
                .WR_DATA_25(w_mux_25.WR_DATA),
                .WR_SRAM_NUM_25(w_mux_25.WR_SRAM_NUM),
                .WR_EN_26(w_mux_26.WR_EN),
                .WR_ADDR_26(w_mux_26.WR_ADDR),
                .WR_DATA_26(w_mux_26.WR_DATA),
                .WR_SRAM_NUM_26(w_mux_26.WR_SRAM_NUM),
                .WR_EN_27(w_mux_27.WR_EN),
                .WR_ADDR_27(w_mux_27.WR_ADDR),
                .WR_DATA_27(w_mux_27.WR_DATA),
                .WR_SRAM_NUM_27(w_mux_27.WR_SRAM_NUM),
                .WR_EN_28(w_mux_28.WR_EN),
                .WR_ADDR_28(w_mux_28.WR_ADDR),
                .WR_DATA_28(w_mux_28.WR_DATA),
                .WR_SRAM_NUM_28(w_mux_28.WR_SRAM_NUM),
                .WR_EN_29(w_mux_29.WR_EN),
                .WR_ADDR_29(w_mux_29.WR_ADDR),
                .WR_DATA_29(w_mux_29.WR_DATA),
                .WR_SRAM_NUM_29(w_mux_29.WR_SRAM_NUM),
                .WR_EN_30(w_mux_30.WR_EN),
                .WR_ADDR_30(w_mux_30.WR_ADDR),
                .WR_DATA_30(w_mux_30.WR_DATA),
                .WR_SRAM_NUM_30(w_mux_30.WR_SRAM_NUM),
                .WR_EN_31(w_mux_31.WR_EN),
                .WR_ADDR_31(w_mux_31.WR_ADDR),
                .WR_DATA_31(w_mux_31.WR_DATA),
                .WR_SRAM_NUM_31(w_mux_31.WR_SRAM_NUM),
                .WR_EN_32(w_mux_32.WR_EN),
                .WR_ADDR_32(w_mux_32.WR_ADDR),
                .WR_DATA_32(w_mux_32.WR_DATA),
                .WR_SRAM_NUM_32(w_mux_32.WR_SRAM_NUM),
                .WR_EN_33(w_mux_33.WR_EN),
                .WR_ADDR_33(w_mux_33.WR_ADDR),
                .WR_DATA_33(w_mux_33.WR_DATA),
                .WR_SRAM_NUM_33(w_mux_33.WR_SRAM_NUM),
                .WR_EN_34(w_mux_34.WR_EN),
                .WR_ADDR_34(w_mux_34.WR_ADDR),
                .WR_DATA_34(w_mux_34.WR_DATA),
                .WR_SRAM_NUM_34(w_mux_34.WR_SRAM_NUM),
                .WR_EN_35(w_mux_35.WR_EN),
                .WR_ADDR_35(w_mux_35.WR_ADDR),
                .WR_DATA_35(w_mux_35.WR_DATA),
                .WR_SRAM_NUM_35(w_mux_35.WR_SRAM_NUM),
                .WR_EN_36(w_mux_36.WR_EN),
                .WR_ADDR_36(w_mux_36.WR_ADDR),
                .WR_DATA_36(w_mux_36.WR_DATA),
                .WR_SRAM_NUM_36(w_mux_36.WR_SRAM_NUM),
                .WR_EN_37(w_mux_37.WR_EN),
                .WR_ADDR_37(w_mux_37.WR_ADDR),
                .WR_DATA_37(w_mux_37.WR_DATA),
                .WR_SRAM_NUM_37(w_mux_37.WR_SRAM_NUM),
                .WR_EN_38(w_mux_38.WR_EN),
                .WR_ADDR_38(w_mux_38.WR_ADDR),
                .WR_DATA_38(w_mux_38.WR_DATA),
                .WR_SRAM_NUM_38(w_mux_38.WR_SRAM_NUM),
                .WR_EN_39(w_mux_39.WR_EN),
                .WR_ADDR_39(w_mux_39.WR_ADDR),
                .WR_DATA_39(w_mux_39.WR_DATA),
                .WR_SRAM_NUM_39(w_mux_39.WR_SRAM_NUM),
                .WR_EN_40(w_mux_40.WR_EN),
                .WR_ADDR_40(w_mux_40.WR_ADDR),
                .WR_DATA_40(w_mux_40.WR_DATA),
                .WR_SRAM_NUM_40(w_mux_40.WR_SRAM_NUM),
                .WR_EN_41(w_mux_41.WR_EN),
                .WR_ADDR_41(w_mux_41.WR_ADDR),
                .WR_DATA_41(w_mux_41.WR_DATA),
                .WR_SRAM_NUM_41(w_mux_41.WR_SRAM_NUM),
                .WR_EN_42(w_mux_42.WR_EN),
                .WR_ADDR_42(w_mux_42.WR_ADDR),
                .WR_DATA_42(w_mux_42.WR_DATA),
                .WR_SRAM_NUM_42(w_mux_42.WR_SRAM_NUM),
                .WR_EN_43(w_mux_43.WR_EN),
                .WR_ADDR_43(w_mux_43.WR_ADDR),
                .WR_DATA_43(w_mux_43.WR_DATA),
                .WR_SRAM_NUM_43(w_mux_43.WR_SRAM_NUM),
                .WR_EN_44(w_mux_44.WR_EN),
                .WR_ADDR_44(w_mux_44.WR_ADDR),
                .WR_DATA_44(w_mux_44.WR_DATA),
                .WR_SRAM_NUM_44(w_mux_44.WR_SRAM_NUM),
                .WR_EN_45(w_mux_45.WR_EN),
                .WR_ADDR_45(w_mux_45.WR_ADDR),
                .WR_DATA_45(w_mux_45.WR_DATA),
                .WR_SRAM_NUM_45(w_mux_45.WR_SRAM_NUM),
                .WR_EN_46(w_mux_46.WR_EN),
                .WR_ADDR_46(w_mux_46.WR_ADDR),
                .WR_DATA_46(w_mux_46.WR_DATA),
                .WR_SRAM_NUM_46(w_mux_46.WR_SRAM_NUM),
                .WR_EN_47(w_mux_47.WR_EN),
                .WR_ADDR_47(w_mux_47.WR_ADDR),
                .WR_DATA_47(w_mux_47.WR_DATA),
                .WR_SRAM_NUM_47(w_mux_47.WR_SRAM_NUM),
                .W_DATA(sram_mux_15.W_DATA),
                .W_ADDR(sram_mux_15.W_ADDR),
                .WR(sram_mux_15.WR)
            );

rdaddr_decoder rdaddr_decoder_u_0(
    .ADDR(r_mux_0.RD_ADDR),
    .SRAM_NUM(SRAM_NUM_0),
    .SRAM_ADDR(SRAM_ADDR_0)
);
rdaddr_decoder rdaddr_decoder_u_1(
    .ADDR(r_mux_1.RD_ADDR),
    .SRAM_NUM(SRAM_NUM_1),
    .SRAM_ADDR(SRAM_ADDR_1)
);
rdaddr_decoder rdaddr_decoder_u_2(
    .ADDR(r_mux_2.RD_ADDR),
    .SRAM_NUM(SRAM_NUM_2),
    .SRAM_ADDR(SRAM_ADDR_2)
);
rdaddr_decoder rdaddr_decoder_u_3(
    .ADDR(r_mux_3.RD_ADDR),
    .SRAM_NUM(SRAM_NUM_3),
    .SRAM_ADDR(SRAM_ADDR_3)
);
rdaddr_decoder rdaddr_decoder_u_4(
    .ADDR(r_mux_4.RD_ADDR),
    .SRAM_NUM(SRAM_NUM_4),
    .SRAM_ADDR(SRAM_ADDR_4)
);
rdaddr_decoder rdaddr_decoder_u_5(
    .ADDR(r_mux_5.RD_ADDR),
    .SRAM_NUM(SRAM_NUM_5),
    .SRAM_ADDR(SRAM_ADDR_5)
);
rdaddr_decoder rdaddr_decoder_u_6(
    .ADDR(r_mux_6.RD_ADDR),
    .SRAM_NUM(SRAM_NUM_6),
    .SRAM_ADDR(SRAM_ADDR_6)
);
rdaddr_decoder rdaddr_decoder_u_7(
    .ADDR(r_mux_7.RD_ADDR),
    .SRAM_NUM(SRAM_NUM_7),
    .SRAM_ADDR(SRAM_ADDR_7)
);
rdaddr_decoder rdaddr_decoder_u_8(
    .ADDR(r_mux_8.RD_ADDR),
    .SRAM_NUM(SRAM_NUM_8),
    .SRAM_ADDR(SRAM_ADDR_8)
);
rdaddr_decoder rdaddr_decoder_u_9(
    .ADDR(r_mux_9.RD_ADDR),
    .SRAM_NUM(SRAM_NUM_9),
    .SRAM_ADDR(SRAM_ADDR_9)
);
rdaddr_decoder rdaddr_decoder_u_10(
    .ADDR(r_mux_10.RD_ADDR),
    .SRAM_NUM(SRAM_NUM_10),
    .SRAM_ADDR(SRAM_ADDR_10)
);
rdaddr_decoder rdaddr_decoder_u_11(
    .ADDR(r_mux_11.RD_ADDR),
    .SRAM_NUM(SRAM_NUM_11),
    .SRAM_ADDR(SRAM_ADDR_11)
);
rdaddr_decoder rdaddr_decoder_u_12(
    .ADDR(r_mux_12.RD_ADDR),
    .SRAM_NUM(SRAM_NUM_12),
    .SRAM_ADDR(SRAM_ADDR_12)
);
rdaddr_decoder rdaddr_decoder_u_13(
    .ADDR(r_mux_13.RD_ADDR),
    .SRAM_NUM(SRAM_NUM_13),
    .SRAM_ADDR(SRAM_ADDR_13)
);
rdaddr_decoder rdaddr_decoder_u_14(
    .ADDR(r_mux_14.RD_ADDR),
    .SRAM_NUM(SRAM_NUM_14),
    .SRAM_ADDR(SRAM_ADDR_14)
);
rdaddr_decoder rdaddr_decoder_u_15(
    .ADDR(r_mux_15.RD_ADDR),
    .SRAM_NUM(SRAM_NUM_15),
    .SRAM_ADDR(SRAM_ADDR_15)
);

rd_sram_ctrl#(.RD_SRAM_num(16))
            rd_sram_ctrl_u_0(
                .RD_EN_0(r_mux_0.RD_EN),
                .RD_EN_1(r_mux_1.RD_EN),
                .RD_EN_2(r_mux_2.RD_EN),
                .RD_EN_3(r_mux_3.RD_EN),
                .RD_EN_4(r_mux_4.RD_EN),
                .RD_EN_5(r_mux_5.RD_EN),
                .RD_EN_6(r_mux_6.RD_EN),
                .RD_EN_7(r_mux_7.RD_EN),
                .RD_EN_8(r_mux_8.RD_EN),
                .RD_EN_9(r_mux_9.RD_EN),
                .RD_EN_10(r_mux_10.RD_EN),
                .RD_EN_11(r_mux_11.RD_EN),
                .RD_EN_12(r_mux_12.RD_EN),
                .RD_EN_13(r_mux_13.RD_EN),
                .RD_EN_14(r_mux_14.RD_EN),
                .RD_EN_15(r_mux_15.RD_EN),

                .SRAM_NUM_0(SRAM_NUM_0),
                .SRAM_NUM_1(SRAM_NUM_1),
                .SRAM_NUM_2(SRAM_NUM_2),
                .SRAM_NUM_3(SRAM_NUM_3),
                .SRAM_NUM_4(SRAM_NUM_4),
                .SRAM_NUM_5(SRAM_NUM_5),
                .SRAM_NUM_6(SRAM_NUM_6),
                .SRAM_NUM_7(SRAM_NUM_7),
                .SRAM_NUM_8(SRAM_NUM_8),
                .SRAM_NUM_9(SRAM_NUM_9),
                .SRAM_NUM_10(SRAM_NUM_10),
                .SRAM_NUM_11(SRAM_NUM_11),
                .SRAM_NUM_12(SRAM_NUM_12),
                .SRAM_NUM_13(SRAM_NUM_13),
                .SRAM_NUM_14(SRAM_NUM_14),
                .SRAM_NUM_15(SRAM_NUM_15),

                .ADDR_0(SRAM_ADDR_0),
                .ADDR_1(SRAM_ADDR_1),
                .ADDR_2(SRAM_ADDR_2),
                .ADDR_3(SRAM_ADDR_3),
                .ADDR_4(SRAM_ADDR_4),
                .ADDR_5(SRAM_ADDR_5),
                .ADDR_6(SRAM_ADDR_6),
                .ADDR_7(SRAM_ADDR_7),
                .ADDR_8(SRAM_ADDR_8),
                .ADDR_9(SRAM_ADDR_9),
                .ADDR_10(SRAM_ADDR_10),
                .ADDR_11(SRAM_ADDR_11),
                .ADDR_12(SRAM_ADDR_12),
                .ADDR_13(SRAM_ADDR_13),
                .ADDR_14(SRAM_ADDR_14),
                .ADDR_15(SRAM_ADDR_15),
                
                .ADDR_O(ADDR_O_0),
                .RD(RD_0)
            );
rd_sram_ctrl#(.RD_SRAM_num(17))
            rd_sram_ctrl_u_1(
                .RD_EN_0(r_mux_0.RD_EN),
                .RD_EN_1(r_mux_1.RD_EN),
                .RD_EN_2(r_mux_2.RD_EN),
                .RD_EN_3(r_mux_3.RD_EN),
                .RD_EN_4(r_mux_4.RD_EN),
                .RD_EN_5(r_mux_5.RD_EN),
                .RD_EN_6(r_mux_6.RD_EN),
                .RD_EN_7(r_mux_7.RD_EN),
                .RD_EN_8(r_mux_8.RD_EN),
                .RD_EN_9(r_mux_9.RD_EN),
                .RD_EN_10(r_mux_10.RD_EN),
                .RD_EN_11(r_mux_11.RD_EN),
                .RD_EN_12(r_mux_12.RD_EN),
                .RD_EN_13(r_mux_13.RD_EN),
                .RD_EN_14(r_mux_14.RD_EN),
                .RD_EN_15(r_mux_15.RD_EN),

                .SRAM_NUM_0(SRAM_NUM_0),
                .SRAM_NUM_1(SRAM_NUM_1),
                .SRAM_NUM_2(SRAM_NUM_2),
                .SRAM_NUM_3(SRAM_NUM_3),
                .SRAM_NUM_4(SRAM_NUM_4),
                .SRAM_NUM_5(SRAM_NUM_5),
                .SRAM_NUM_6(SRAM_NUM_6),
                .SRAM_NUM_7(SRAM_NUM_7),
                .SRAM_NUM_8(SRAM_NUM_8),
                .SRAM_NUM_9(SRAM_NUM_9),
                .SRAM_NUM_10(SRAM_NUM_10),
                .SRAM_NUM_11(SRAM_NUM_11),
                .SRAM_NUM_12(SRAM_NUM_12),
                .SRAM_NUM_13(SRAM_NUM_13),
                .SRAM_NUM_14(SRAM_NUM_14),
                .SRAM_NUM_15(SRAM_NUM_15),

                .ADDR_0(SRAM_ADDR_0),
                .ADDR_1(SRAM_ADDR_1),
                .ADDR_2(SRAM_ADDR_2),
                .ADDR_3(SRAM_ADDR_3),
                .ADDR_4(SRAM_ADDR_4),
                .ADDR_5(SRAM_ADDR_5),
                .ADDR_6(SRAM_ADDR_6),
                .ADDR_7(SRAM_ADDR_7),
                .ADDR_8(SRAM_ADDR_8),
                .ADDR_9(SRAM_ADDR_9),
                .ADDR_10(SRAM_ADDR_10),
                .ADDR_11(SRAM_ADDR_11),
                .ADDR_12(SRAM_ADDR_12),
                .ADDR_13(SRAM_ADDR_13),
                .ADDR_14(SRAM_ADDR_14),
                .ADDR_15(SRAM_ADDR_15),
                
                .ADDR_O(ADDR_O_1),
                .RD(RD_1)
            );
rd_sram_ctrl#(.RD_SRAM_num(18))
            rd_sram_ctrl_u_2(
                .RD_EN_0(r_mux_0.RD_EN),
                .RD_EN_1(r_mux_1.RD_EN),
                .RD_EN_2(r_mux_2.RD_EN),
                .RD_EN_3(r_mux_3.RD_EN),
                .RD_EN_4(r_mux_4.RD_EN),
                .RD_EN_5(r_mux_5.RD_EN),
                .RD_EN_6(r_mux_6.RD_EN),
                .RD_EN_7(r_mux_7.RD_EN),
                .RD_EN_8(r_mux_8.RD_EN),
                .RD_EN_9(r_mux_9.RD_EN),
                .RD_EN_10(r_mux_10.RD_EN),
                .RD_EN_11(r_mux_11.RD_EN),
                .RD_EN_12(r_mux_12.RD_EN),
                .RD_EN_13(r_mux_13.RD_EN),
                .RD_EN_14(r_mux_14.RD_EN),
                .RD_EN_15(r_mux_15.RD_EN),

                .SRAM_NUM_0(SRAM_NUM_0),
                .SRAM_NUM_1(SRAM_NUM_1),
                .SRAM_NUM_2(SRAM_NUM_2),
                .SRAM_NUM_3(SRAM_NUM_3),
                .SRAM_NUM_4(SRAM_NUM_4),
                .SRAM_NUM_5(SRAM_NUM_5),
                .SRAM_NUM_6(SRAM_NUM_6),
                .SRAM_NUM_7(SRAM_NUM_7),
                .SRAM_NUM_8(SRAM_NUM_8),
                .SRAM_NUM_9(SRAM_NUM_9),
                .SRAM_NUM_10(SRAM_NUM_10),
                .SRAM_NUM_11(SRAM_NUM_11),
                .SRAM_NUM_12(SRAM_NUM_12),
                .SRAM_NUM_13(SRAM_NUM_13),
                .SRAM_NUM_14(SRAM_NUM_14),
                .SRAM_NUM_15(SRAM_NUM_15),

                .ADDR_0(SRAM_ADDR_0),
                .ADDR_1(SRAM_ADDR_1),
                .ADDR_2(SRAM_ADDR_2),
                .ADDR_3(SRAM_ADDR_3),
                .ADDR_4(SRAM_ADDR_4),
                .ADDR_5(SRAM_ADDR_5),
                .ADDR_6(SRAM_ADDR_6),
                .ADDR_7(SRAM_ADDR_7),
                .ADDR_8(SRAM_ADDR_8),
                .ADDR_9(SRAM_ADDR_9),
                .ADDR_10(SRAM_ADDR_10),
                .ADDR_11(SRAM_ADDR_11),
                .ADDR_12(SRAM_ADDR_12),
                .ADDR_13(SRAM_ADDR_13),
                .ADDR_14(SRAM_ADDR_14),
                .ADDR_15(SRAM_ADDR_15),
                
                .ADDR_O(ADDR_O_2),
                .RD(RD_2)
            );
rd_sram_ctrl#(.RD_SRAM_num(19))
            rd_sram_ctrl_u_3(
                .RD_EN_0(r_mux_0.RD_EN),
                .RD_EN_1(r_mux_1.RD_EN),
                .RD_EN_2(r_mux_2.RD_EN),
                .RD_EN_3(r_mux_3.RD_EN),
                .RD_EN_4(r_mux_4.RD_EN),
                .RD_EN_5(r_mux_5.RD_EN),
                .RD_EN_6(r_mux_6.RD_EN),
                .RD_EN_7(r_mux_7.RD_EN),
                .RD_EN_8(r_mux_8.RD_EN),
                .RD_EN_9(r_mux_9.RD_EN),
                .RD_EN_10(r_mux_10.RD_EN),
                .RD_EN_11(r_mux_11.RD_EN),
                .RD_EN_12(r_mux_12.RD_EN),
                .RD_EN_13(r_mux_13.RD_EN),
                .RD_EN_14(r_mux_14.RD_EN),
                .RD_EN_15(r_mux_15.RD_EN),

                .SRAM_NUM_0(SRAM_NUM_0),
                .SRAM_NUM_1(SRAM_NUM_1),
                .SRAM_NUM_2(SRAM_NUM_2),
                .SRAM_NUM_3(SRAM_NUM_3),
                .SRAM_NUM_4(SRAM_NUM_4),
                .SRAM_NUM_5(SRAM_NUM_5),
                .SRAM_NUM_6(SRAM_NUM_6),
                .SRAM_NUM_7(SRAM_NUM_7),
                .SRAM_NUM_8(SRAM_NUM_8),
                .SRAM_NUM_9(SRAM_NUM_9),
                .SRAM_NUM_10(SRAM_NUM_10),
                .SRAM_NUM_11(SRAM_NUM_11),
                .SRAM_NUM_12(SRAM_NUM_12),
                .SRAM_NUM_13(SRAM_NUM_13),
                .SRAM_NUM_14(SRAM_NUM_14),
                .SRAM_NUM_15(SRAM_NUM_15),

                .ADDR_0(SRAM_ADDR_0),
                .ADDR_1(SRAM_ADDR_1),
                .ADDR_2(SRAM_ADDR_2),
                .ADDR_3(SRAM_ADDR_3),
                .ADDR_4(SRAM_ADDR_4),
                .ADDR_5(SRAM_ADDR_5),
                .ADDR_6(SRAM_ADDR_6),
                .ADDR_7(SRAM_ADDR_7),
                .ADDR_8(SRAM_ADDR_8),
                .ADDR_9(SRAM_ADDR_9),
                .ADDR_10(SRAM_ADDR_10),
                .ADDR_11(SRAM_ADDR_11),
                .ADDR_12(SRAM_ADDR_12),
                .ADDR_13(SRAM_ADDR_13),
                .ADDR_14(SRAM_ADDR_14),
                .ADDR_15(SRAM_ADDR_15),
                
                .ADDR_O(ADDR_O_3),
                .RD(RD_3)
            );
rd_sram_ctrl#(.RD_SRAM_num(20))
            rd_sram_ctrl_u_4(
                .RD_EN_0(r_mux_0.RD_EN),
                .RD_EN_1(r_mux_1.RD_EN),
                .RD_EN_2(r_mux_2.RD_EN),
                .RD_EN_3(r_mux_3.RD_EN),
                .RD_EN_4(r_mux_4.RD_EN),
                .RD_EN_5(r_mux_5.RD_EN),
                .RD_EN_6(r_mux_6.RD_EN),
                .RD_EN_7(r_mux_7.RD_EN),
                .RD_EN_8(r_mux_8.RD_EN),
                .RD_EN_9(r_mux_9.RD_EN),
                .RD_EN_10(r_mux_10.RD_EN),
                .RD_EN_11(r_mux_11.RD_EN),
                .RD_EN_12(r_mux_12.RD_EN),
                .RD_EN_13(r_mux_13.RD_EN),
                .RD_EN_14(r_mux_14.RD_EN),
                .RD_EN_15(r_mux_15.RD_EN),

                .SRAM_NUM_0(SRAM_NUM_0),
                .SRAM_NUM_1(SRAM_NUM_1),
                .SRAM_NUM_2(SRAM_NUM_2),
                .SRAM_NUM_3(SRAM_NUM_3),
                .SRAM_NUM_4(SRAM_NUM_4),
                .SRAM_NUM_5(SRAM_NUM_5),
                .SRAM_NUM_6(SRAM_NUM_6),
                .SRAM_NUM_7(SRAM_NUM_7),
                .SRAM_NUM_8(SRAM_NUM_8),
                .SRAM_NUM_9(SRAM_NUM_9),
                .SRAM_NUM_10(SRAM_NUM_10),
                .SRAM_NUM_11(SRAM_NUM_11),
                .SRAM_NUM_12(SRAM_NUM_12),
                .SRAM_NUM_13(SRAM_NUM_13),
                .SRAM_NUM_14(SRAM_NUM_14),
                .SRAM_NUM_15(SRAM_NUM_15),

                .ADDR_0(SRAM_ADDR_0),
                .ADDR_1(SRAM_ADDR_1),
                .ADDR_2(SRAM_ADDR_2),
                .ADDR_3(SRAM_ADDR_3),
                .ADDR_4(SRAM_ADDR_4),
                .ADDR_5(SRAM_ADDR_5),
                .ADDR_6(SRAM_ADDR_6),
                .ADDR_7(SRAM_ADDR_7),
                .ADDR_8(SRAM_ADDR_8),
                .ADDR_9(SRAM_ADDR_9),
                .ADDR_10(SRAM_ADDR_10),
                .ADDR_11(SRAM_ADDR_11),
                .ADDR_12(SRAM_ADDR_12),
                .ADDR_13(SRAM_ADDR_13),
                .ADDR_14(SRAM_ADDR_14),
                .ADDR_15(SRAM_ADDR_15),
                
                .ADDR_O(ADDR_O_4),
                .RD(RD_4)
            );
rd_sram_ctrl#(.RD_SRAM_num(21))
            rd_sram_ctrl_u_5(
                .RD_EN_0(r_mux_0.RD_EN),
                .RD_EN_1(r_mux_1.RD_EN),
                .RD_EN_2(r_mux_2.RD_EN),
                .RD_EN_3(r_mux_3.RD_EN),
                .RD_EN_4(r_mux_4.RD_EN),
                .RD_EN_5(r_mux_5.RD_EN),
                .RD_EN_6(r_mux_6.RD_EN),
                .RD_EN_7(r_mux_7.RD_EN),
                .RD_EN_8(r_mux_8.RD_EN),
                .RD_EN_9(r_mux_9.RD_EN),
                .RD_EN_10(r_mux_10.RD_EN),
                .RD_EN_11(r_mux_11.RD_EN),
                .RD_EN_12(r_mux_12.RD_EN),
                .RD_EN_13(r_mux_13.RD_EN),
                .RD_EN_14(r_mux_14.RD_EN),
                .RD_EN_15(r_mux_15.RD_EN),

                .SRAM_NUM_0(SRAM_NUM_0),
                .SRAM_NUM_1(SRAM_NUM_1),
                .SRAM_NUM_2(SRAM_NUM_2),
                .SRAM_NUM_3(SRAM_NUM_3),
                .SRAM_NUM_4(SRAM_NUM_4),
                .SRAM_NUM_5(SRAM_NUM_5),
                .SRAM_NUM_6(SRAM_NUM_6),
                .SRAM_NUM_7(SRAM_NUM_7),
                .SRAM_NUM_8(SRAM_NUM_8),
                .SRAM_NUM_9(SRAM_NUM_9),
                .SRAM_NUM_10(SRAM_NUM_10),
                .SRAM_NUM_11(SRAM_NUM_11),
                .SRAM_NUM_12(SRAM_NUM_12),
                .SRAM_NUM_13(SRAM_NUM_13),
                .SRAM_NUM_14(SRAM_NUM_14),
                .SRAM_NUM_15(SRAM_NUM_15),

                .ADDR_0(SRAM_ADDR_0),
                .ADDR_1(SRAM_ADDR_1),
                .ADDR_2(SRAM_ADDR_2),
                .ADDR_3(SRAM_ADDR_3),
                .ADDR_4(SRAM_ADDR_4),
                .ADDR_5(SRAM_ADDR_5),
                .ADDR_6(SRAM_ADDR_6),
                .ADDR_7(SRAM_ADDR_7),
                .ADDR_8(SRAM_ADDR_8),
                .ADDR_9(SRAM_ADDR_9),
                .ADDR_10(SRAM_ADDR_10),
                .ADDR_11(SRAM_ADDR_11),
                .ADDR_12(SRAM_ADDR_12),
                .ADDR_13(SRAM_ADDR_13),
                .ADDR_14(SRAM_ADDR_14),
                .ADDR_15(SRAM_ADDR_15),
                
                .ADDR_O(ADDR_O_5),
                .RD(RD_5)
            );
rd_sram_ctrl#(.RD_SRAM_num(22))
            rd_sram_ctrl_u_6(
                .RD_EN_0(r_mux_0.RD_EN),
                .RD_EN_1(r_mux_1.RD_EN),
                .RD_EN_2(r_mux_2.RD_EN),
                .RD_EN_3(r_mux_3.RD_EN),
                .RD_EN_4(r_mux_4.RD_EN),
                .RD_EN_5(r_mux_5.RD_EN),
                .RD_EN_6(r_mux_6.RD_EN),
                .RD_EN_7(r_mux_7.RD_EN),
                .RD_EN_8(r_mux_8.RD_EN),
                .RD_EN_9(r_mux_9.RD_EN),
                .RD_EN_10(r_mux_10.RD_EN),
                .RD_EN_11(r_mux_11.RD_EN),
                .RD_EN_12(r_mux_12.RD_EN),
                .RD_EN_13(r_mux_13.RD_EN),
                .RD_EN_14(r_mux_14.RD_EN),
                .RD_EN_15(r_mux_15.RD_EN),

                .SRAM_NUM_0(SRAM_NUM_0),
                .SRAM_NUM_1(SRAM_NUM_1),
                .SRAM_NUM_2(SRAM_NUM_2),
                .SRAM_NUM_3(SRAM_NUM_3),
                .SRAM_NUM_4(SRAM_NUM_4),
                .SRAM_NUM_5(SRAM_NUM_5),
                .SRAM_NUM_6(SRAM_NUM_6),
                .SRAM_NUM_7(SRAM_NUM_7),
                .SRAM_NUM_8(SRAM_NUM_8),
                .SRAM_NUM_9(SRAM_NUM_9),
                .SRAM_NUM_10(SRAM_NUM_10),
                .SRAM_NUM_11(SRAM_NUM_11),
                .SRAM_NUM_12(SRAM_NUM_12),
                .SRAM_NUM_13(SRAM_NUM_13),
                .SRAM_NUM_14(SRAM_NUM_14),
                .SRAM_NUM_15(SRAM_NUM_15),

                .ADDR_0(SRAM_ADDR_0),
                .ADDR_1(SRAM_ADDR_1),
                .ADDR_2(SRAM_ADDR_2),
                .ADDR_3(SRAM_ADDR_3),
                .ADDR_4(SRAM_ADDR_4),
                .ADDR_5(SRAM_ADDR_5),
                .ADDR_6(SRAM_ADDR_6),
                .ADDR_7(SRAM_ADDR_7),
                .ADDR_8(SRAM_ADDR_8),
                .ADDR_9(SRAM_ADDR_9),
                .ADDR_10(SRAM_ADDR_10),
                .ADDR_11(SRAM_ADDR_11),
                .ADDR_12(SRAM_ADDR_12),
                .ADDR_13(SRAM_ADDR_13),
                .ADDR_14(SRAM_ADDR_14),
                .ADDR_15(SRAM_ADDR_15),
                
                .ADDR_O(ADDR_O_6),
                .RD(RD_6)
            );
rd_sram_ctrl#(.RD_SRAM_num(23))
            rd_sram_ctrl_u_7(
                .RD_EN_0(r_mux_0.RD_EN),
                .RD_EN_1(r_mux_1.RD_EN),
                .RD_EN_2(r_mux_2.RD_EN),
                .RD_EN_3(r_mux_3.RD_EN),
                .RD_EN_4(r_mux_4.RD_EN),
                .RD_EN_5(r_mux_5.RD_EN),
                .RD_EN_6(r_mux_6.RD_EN),
                .RD_EN_7(r_mux_7.RD_EN),
                .RD_EN_8(r_mux_8.RD_EN),
                .RD_EN_9(r_mux_9.RD_EN),
                .RD_EN_10(r_mux_10.RD_EN),
                .RD_EN_11(r_mux_11.RD_EN),
                .RD_EN_12(r_mux_12.RD_EN),
                .RD_EN_13(r_mux_13.RD_EN),
                .RD_EN_14(r_mux_14.RD_EN),
                .RD_EN_15(r_mux_15.RD_EN),

                .SRAM_NUM_0(SRAM_NUM_0),
                .SRAM_NUM_1(SRAM_NUM_1),
                .SRAM_NUM_2(SRAM_NUM_2),
                .SRAM_NUM_3(SRAM_NUM_3),
                .SRAM_NUM_4(SRAM_NUM_4),
                .SRAM_NUM_5(SRAM_NUM_5),
                .SRAM_NUM_6(SRAM_NUM_6),
                .SRAM_NUM_7(SRAM_NUM_7),
                .SRAM_NUM_8(SRAM_NUM_8),
                .SRAM_NUM_9(SRAM_NUM_9),
                .SRAM_NUM_10(SRAM_NUM_10),
                .SRAM_NUM_11(SRAM_NUM_11),
                .SRAM_NUM_12(SRAM_NUM_12),
                .SRAM_NUM_13(SRAM_NUM_13),
                .SRAM_NUM_14(SRAM_NUM_14),
                .SRAM_NUM_15(SRAM_NUM_15),

                .ADDR_0(SRAM_ADDR_0),
                .ADDR_1(SRAM_ADDR_1),
                .ADDR_2(SRAM_ADDR_2),
                .ADDR_3(SRAM_ADDR_3),
                .ADDR_4(SRAM_ADDR_4),
                .ADDR_5(SRAM_ADDR_5),
                .ADDR_6(SRAM_ADDR_6),
                .ADDR_7(SRAM_ADDR_7),
                .ADDR_8(SRAM_ADDR_8),
                .ADDR_9(SRAM_ADDR_9),
                .ADDR_10(SRAM_ADDR_10),
                .ADDR_11(SRAM_ADDR_11),
                .ADDR_12(SRAM_ADDR_12),
                .ADDR_13(SRAM_ADDR_13),
                .ADDR_14(SRAM_ADDR_14),
                .ADDR_15(SRAM_ADDR_15),
                
                .ADDR_O(ADDR_O_7),
                .RD(RD_7)
            );
rd_sram_ctrl#(.RD_SRAM_num(24))
            rd_sram_ctrl_u_8(
                .RD_EN_0(r_mux_0.RD_EN),
                .RD_EN_1(r_mux_1.RD_EN),
                .RD_EN_2(r_mux_2.RD_EN),
                .RD_EN_3(r_mux_3.RD_EN),
                .RD_EN_4(r_mux_4.RD_EN),
                .RD_EN_5(r_mux_5.RD_EN),
                .RD_EN_6(r_mux_6.RD_EN),
                .RD_EN_7(r_mux_7.RD_EN),
                .RD_EN_8(r_mux_8.RD_EN),
                .RD_EN_9(r_mux_9.RD_EN),
                .RD_EN_10(r_mux_10.RD_EN),
                .RD_EN_11(r_mux_11.RD_EN),
                .RD_EN_12(r_mux_12.RD_EN),
                .RD_EN_13(r_mux_13.RD_EN),
                .RD_EN_14(r_mux_14.RD_EN),
                .RD_EN_15(r_mux_15.RD_EN),

                .SRAM_NUM_0(SRAM_NUM_0),
                .SRAM_NUM_1(SRAM_NUM_1),
                .SRAM_NUM_2(SRAM_NUM_2),
                .SRAM_NUM_3(SRAM_NUM_3),
                .SRAM_NUM_4(SRAM_NUM_4),
                .SRAM_NUM_5(SRAM_NUM_5),
                .SRAM_NUM_6(SRAM_NUM_6),
                .SRAM_NUM_7(SRAM_NUM_7),
                .SRAM_NUM_8(SRAM_NUM_8),
                .SRAM_NUM_9(SRAM_NUM_9),
                .SRAM_NUM_10(SRAM_NUM_10),
                .SRAM_NUM_11(SRAM_NUM_11),
                .SRAM_NUM_12(SRAM_NUM_12),
                .SRAM_NUM_13(SRAM_NUM_13),
                .SRAM_NUM_14(SRAM_NUM_14),
                .SRAM_NUM_15(SRAM_NUM_15),

                .ADDR_0(SRAM_ADDR_0),
                .ADDR_1(SRAM_ADDR_1),
                .ADDR_2(SRAM_ADDR_2),
                .ADDR_3(SRAM_ADDR_3),
                .ADDR_4(SRAM_ADDR_4),
                .ADDR_5(SRAM_ADDR_5),
                .ADDR_6(SRAM_ADDR_6),
                .ADDR_7(SRAM_ADDR_7),
                .ADDR_8(SRAM_ADDR_8),
                .ADDR_9(SRAM_ADDR_9),
                .ADDR_10(SRAM_ADDR_10),
                .ADDR_11(SRAM_ADDR_11),
                .ADDR_12(SRAM_ADDR_12),
                .ADDR_13(SRAM_ADDR_13),
                .ADDR_14(SRAM_ADDR_14),
                .ADDR_15(SRAM_ADDR_15),
                
                .ADDR_O(ADDR_O_8),
                .RD(RD_8)
            );
rd_sram_ctrl#(.RD_SRAM_num(25))
            rd_sram_ctrl_u_9(
                .RD_EN_0(r_mux_0.RD_EN),
                .RD_EN_1(r_mux_1.RD_EN),
                .RD_EN_2(r_mux_2.RD_EN),
                .RD_EN_3(r_mux_3.RD_EN),
                .RD_EN_4(r_mux_4.RD_EN),
                .RD_EN_5(r_mux_5.RD_EN),
                .RD_EN_6(r_mux_6.RD_EN),
                .RD_EN_7(r_mux_7.RD_EN),
                .RD_EN_8(r_mux_8.RD_EN),
                .RD_EN_9(r_mux_9.RD_EN),
                .RD_EN_10(r_mux_10.RD_EN),
                .RD_EN_11(r_mux_11.RD_EN),
                .RD_EN_12(r_mux_12.RD_EN),
                .RD_EN_13(r_mux_13.RD_EN),
                .RD_EN_14(r_mux_14.RD_EN),
                .RD_EN_15(r_mux_15.RD_EN),

                .SRAM_NUM_0(SRAM_NUM_0),
                .SRAM_NUM_1(SRAM_NUM_1),
                .SRAM_NUM_2(SRAM_NUM_2),
                .SRAM_NUM_3(SRAM_NUM_3),
                .SRAM_NUM_4(SRAM_NUM_4),
                .SRAM_NUM_5(SRAM_NUM_5),
                .SRAM_NUM_6(SRAM_NUM_6),
                .SRAM_NUM_7(SRAM_NUM_7),
                .SRAM_NUM_8(SRAM_NUM_8),
                .SRAM_NUM_9(SRAM_NUM_9),
                .SRAM_NUM_10(SRAM_NUM_10),
                .SRAM_NUM_11(SRAM_NUM_11),
                .SRAM_NUM_12(SRAM_NUM_12),
                .SRAM_NUM_13(SRAM_NUM_13),
                .SRAM_NUM_14(SRAM_NUM_14),
                .SRAM_NUM_15(SRAM_NUM_15),

                .ADDR_0(SRAM_ADDR_0),
                .ADDR_1(SRAM_ADDR_1),
                .ADDR_2(SRAM_ADDR_2),
                .ADDR_3(SRAM_ADDR_3),
                .ADDR_4(SRAM_ADDR_4),
                .ADDR_5(SRAM_ADDR_5),
                .ADDR_6(SRAM_ADDR_6),
                .ADDR_7(SRAM_ADDR_7),
                .ADDR_8(SRAM_ADDR_8),
                .ADDR_9(SRAM_ADDR_9),
                .ADDR_10(SRAM_ADDR_10),
                .ADDR_11(SRAM_ADDR_11),
                .ADDR_12(SRAM_ADDR_12),
                .ADDR_13(SRAM_ADDR_13),
                .ADDR_14(SRAM_ADDR_14),
                .ADDR_15(SRAM_ADDR_15),
                
                .ADDR_O(ADDR_O_9),
                .RD(RD_9)
            );
rd_sram_ctrl#(.RD_SRAM_num(26))
            rd_sram_ctrl_u_10(
                .RD_EN_0(r_mux_0.RD_EN),
                .RD_EN_1(r_mux_1.RD_EN),
                .RD_EN_2(r_mux_2.RD_EN),
                .RD_EN_3(r_mux_3.RD_EN),
                .RD_EN_4(r_mux_4.RD_EN),
                .RD_EN_5(r_mux_5.RD_EN),
                .RD_EN_6(r_mux_6.RD_EN),
                .RD_EN_7(r_mux_7.RD_EN),
                .RD_EN_8(r_mux_8.RD_EN),
                .RD_EN_9(r_mux_9.RD_EN),
                .RD_EN_10(r_mux_10.RD_EN),
                .RD_EN_11(r_mux_11.RD_EN),
                .RD_EN_12(r_mux_12.RD_EN),
                .RD_EN_13(r_mux_13.RD_EN),
                .RD_EN_14(r_mux_14.RD_EN),
                .RD_EN_15(r_mux_15.RD_EN),

                .SRAM_NUM_0(SRAM_NUM_0),
                .SRAM_NUM_1(SRAM_NUM_1),
                .SRAM_NUM_2(SRAM_NUM_2),
                .SRAM_NUM_3(SRAM_NUM_3),
                .SRAM_NUM_4(SRAM_NUM_4),
                .SRAM_NUM_5(SRAM_NUM_5),
                .SRAM_NUM_6(SRAM_NUM_6),
                .SRAM_NUM_7(SRAM_NUM_7),
                .SRAM_NUM_8(SRAM_NUM_8),
                .SRAM_NUM_9(SRAM_NUM_9),
                .SRAM_NUM_10(SRAM_NUM_10),
                .SRAM_NUM_11(SRAM_NUM_11),
                .SRAM_NUM_12(SRAM_NUM_12),
                .SRAM_NUM_13(SRAM_NUM_13),
                .SRAM_NUM_14(SRAM_NUM_14),
                .SRAM_NUM_15(SRAM_NUM_15),

                .ADDR_0(SRAM_ADDR_0),
                .ADDR_1(SRAM_ADDR_1),
                .ADDR_2(SRAM_ADDR_2),
                .ADDR_3(SRAM_ADDR_3),
                .ADDR_4(SRAM_ADDR_4),
                .ADDR_5(SRAM_ADDR_5),
                .ADDR_6(SRAM_ADDR_6),
                .ADDR_7(SRAM_ADDR_7),
                .ADDR_8(SRAM_ADDR_8),
                .ADDR_9(SRAM_ADDR_9),
                .ADDR_10(SRAM_ADDR_10),
                .ADDR_11(SRAM_ADDR_11),
                .ADDR_12(SRAM_ADDR_12),
                .ADDR_13(SRAM_ADDR_13),
                .ADDR_14(SRAM_ADDR_14),
                .ADDR_15(SRAM_ADDR_15),
                
                .ADDR_O(ADDR_O_10),
                .RD(RD_10)
            );
rd_sram_ctrl#(.RD_SRAM_num(27))
            rd_sram_ctrl_u_11(
                .RD_EN_0(r_mux_0.RD_EN),
                .RD_EN_1(r_mux_1.RD_EN),
                .RD_EN_2(r_mux_2.RD_EN),
                .RD_EN_3(r_mux_3.RD_EN),
                .RD_EN_4(r_mux_4.RD_EN),
                .RD_EN_5(r_mux_5.RD_EN),
                .RD_EN_6(r_mux_6.RD_EN),
                .RD_EN_7(r_mux_7.RD_EN),
                .RD_EN_8(r_mux_8.RD_EN),
                .RD_EN_9(r_mux_9.RD_EN),
                .RD_EN_10(r_mux_10.RD_EN),
                .RD_EN_11(r_mux_11.RD_EN),
                .RD_EN_12(r_mux_12.RD_EN),
                .RD_EN_13(r_mux_13.RD_EN),
                .RD_EN_14(r_mux_14.RD_EN),
                .RD_EN_15(r_mux_15.RD_EN),

                .SRAM_NUM_0(SRAM_NUM_0),
                .SRAM_NUM_1(SRAM_NUM_1),
                .SRAM_NUM_2(SRAM_NUM_2),
                .SRAM_NUM_3(SRAM_NUM_3),
                .SRAM_NUM_4(SRAM_NUM_4),
                .SRAM_NUM_5(SRAM_NUM_5),
                .SRAM_NUM_6(SRAM_NUM_6),
                .SRAM_NUM_7(SRAM_NUM_7),
                .SRAM_NUM_8(SRAM_NUM_8),
                .SRAM_NUM_9(SRAM_NUM_9),
                .SRAM_NUM_10(SRAM_NUM_10),
                .SRAM_NUM_11(SRAM_NUM_11),
                .SRAM_NUM_12(SRAM_NUM_12),
                .SRAM_NUM_13(SRAM_NUM_13),
                .SRAM_NUM_14(SRAM_NUM_14),
                .SRAM_NUM_15(SRAM_NUM_15),

                .ADDR_0(SRAM_ADDR_0),
                .ADDR_1(SRAM_ADDR_1),
                .ADDR_2(SRAM_ADDR_2),
                .ADDR_3(SRAM_ADDR_3),
                .ADDR_4(SRAM_ADDR_4),
                .ADDR_5(SRAM_ADDR_5),
                .ADDR_6(SRAM_ADDR_6),
                .ADDR_7(SRAM_ADDR_7),
                .ADDR_8(SRAM_ADDR_8),
                .ADDR_9(SRAM_ADDR_9),
                .ADDR_10(SRAM_ADDR_10),
                .ADDR_11(SRAM_ADDR_11),
                .ADDR_12(SRAM_ADDR_12),
                .ADDR_13(SRAM_ADDR_13),
                .ADDR_14(SRAM_ADDR_14),
                .ADDR_15(SRAM_ADDR_15),
                
                .ADDR_O(ADDR_O_11),
                .RD(RD_11)
            );
rd_sram_ctrl#(.RD_SRAM_num(28))
            rd_sram_ctrl_u_12(
                .RD_EN_0(r_mux_0.RD_EN),
                .RD_EN_1(r_mux_1.RD_EN),
                .RD_EN_2(r_mux_2.RD_EN),
                .RD_EN_3(r_mux_3.RD_EN),
                .RD_EN_4(r_mux_4.RD_EN),
                .RD_EN_5(r_mux_5.RD_EN),
                .RD_EN_6(r_mux_6.RD_EN),
                .RD_EN_7(r_mux_7.RD_EN),
                .RD_EN_8(r_mux_8.RD_EN),
                .RD_EN_9(r_mux_9.RD_EN),
                .RD_EN_10(r_mux_10.RD_EN),
                .RD_EN_11(r_mux_11.RD_EN),
                .RD_EN_12(r_mux_12.RD_EN),
                .RD_EN_13(r_mux_13.RD_EN),
                .RD_EN_14(r_mux_14.RD_EN),
                .RD_EN_15(r_mux_15.RD_EN),

                .SRAM_NUM_0(SRAM_NUM_0),
                .SRAM_NUM_1(SRAM_NUM_1),
                .SRAM_NUM_2(SRAM_NUM_2),
                .SRAM_NUM_3(SRAM_NUM_3),
                .SRAM_NUM_4(SRAM_NUM_4),
                .SRAM_NUM_5(SRAM_NUM_5),
                .SRAM_NUM_6(SRAM_NUM_6),
                .SRAM_NUM_7(SRAM_NUM_7),
                .SRAM_NUM_8(SRAM_NUM_8),
                .SRAM_NUM_9(SRAM_NUM_9),
                .SRAM_NUM_10(SRAM_NUM_10),
                .SRAM_NUM_11(SRAM_NUM_11),
                .SRAM_NUM_12(SRAM_NUM_12),
                .SRAM_NUM_13(SRAM_NUM_13),
                .SRAM_NUM_14(SRAM_NUM_14),
                .SRAM_NUM_15(SRAM_NUM_15),

                .ADDR_0(SRAM_ADDR_0),
                .ADDR_1(SRAM_ADDR_1),
                .ADDR_2(SRAM_ADDR_2),
                .ADDR_3(SRAM_ADDR_3),
                .ADDR_4(SRAM_ADDR_4),
                .ADDR_5(SRAM_ADDR_5),
                .ADDR_6(SRAM_ADDR_6),
                .ADDR_7(SRAM_ADDR_7),
                .ADDR_8(SRAM_ADDR_8),
                .ADDR_9(SRAM_ADDR_9),
                .ADDR_10(SRAM_ADDR_10),
                .ADDR_11(SRAM_ADDR_11),
                .ADDR_12(SRAM_ADDR_12),
                .ADDR_13(SRAM_ADDR_13),
                .ADDR_14(SRAM_ADDR_14),
                .ADDR_15(SRAM_ADDR_15),
                
                .ADDR_O(ADDR_O_12),
                .RD(RD_12)
            );
rd_sram_ctrl#(.RD_SRAM_num(29))
            rd_sram_ctrl_u_13(
                .RD_EN_0(r_mux_0.RD_EN),
                .RD_EN_1(r_mux_1.RD_EN),
                .RD_EN_2(r_mux_2.RD_EN),
                .RD_EN_3(r_mux_3.RD_EN),
                .RD_EN_4(r_mux_4.RD_EN),
                .RD_EN_5(r_mux_5.RD_EN),
                .RD_EN_6(r_mux_6.RD_EN),
                .RD_EN_7(r_mux_7.RD_EN),
                .RD_EN_8(r_mux_8.RD_EN),
                .RD_EN_9(r_mux_9.RD_EN),
                .RD_EN_10(r_mux_10.RD_EN),
                .RD_EN_11(r_mux_11.RD_EN),
                .RD_EN_12(r_mux_12.RD_EN),
                .RD_EN_13(r_mux_13.RD_EN),
                .RD_EN_14(r_mux_14.RD_EN),
                .RD_EN_15(r_mux_15.RD_EN),

                .SRAM_NUM_0(SRAM_NUM_0),
                .SRAM_NUM_1(SRAM_NUM_1),
                .SRAM_NUM_2(SRAM_NUM_2),
                .SRAM_NUM_3(SRAM_NUM_3),
                .SRAM_NUM_4(SRAM_NUM_4),
                .SRAM_NUM_5(SRAM_NUM_5),
                .SRAM_NUM_6(SRAM_NUM_6),
                .SRAM_NUM_7(SRAM_NUM_7),
                .SRAM_NUM_8(SRAM_NUM_8),
                .SRAM_NUM_9(SRAM_NUM_9),
                .SRAM_NUM_10(SRAM_NUM_10),
                .SRAM_NUM_11(SRAM_NUM_11),
                .SRAM_NUM_12(SRAM_NUM_12),
                .SRAM_NUM_13(SRAM_NUM_13),
                .SRAM_NUM_14(SRAM_NUM_14),
                .SRAM_NUM_15(SRAM_NUM_15),

                .ADDR_0(SRAM_ADDR_0),
                .ADDR_1(SRAM_ADDR_1),
                .ADDR_2(SRAM_ADDR_2),
                .ADDR_3(SRAM_ADDR_3),
                .ADDR_4(SRAM_ADDR_4),
                .ADDR_5(SRAM_ADDR_5),
                .ADDR_6(SRAM_ADDR_6),
                .ADDR_7(SRAM_ADDR_7),
                .ADDR_8(SRAM_ADDR_8),
                .ADDR_9(SRAM_ADDR_9),
                .ADDR_10(SRAM_ADDR_10),
                .ADDR_11(SRAM_ADDR_11),
                .ADDR_12(SRAM_ADDR_12),
                .ADDR_13(SRAM_ADDR_13),
                .ADDR_14(SRAM_ADDR_14),
                .ADDR_15(SRAM_ADDR_15),
                
                .ADDR_O(ADDR_O_13),
                .RD(RD_13)
            );
rd_sram_ctrl#(.RD_SRAM_num(30))
            rd_sram_ctrl_u_14(
                .RD_EN_0(r_mux_0.RD_EN),
                .RD_EN_1(r_mux_1.RD_EN),
                .RD_EN_2(r_mux_2.RD_EN),
                .RD_EN_3(r_mux_3.RD_EN),
                .RD_EN_4(r_mux_4.RD_EN),
                .RD_EN_5(r_mux_5.RD_EN),
                .RD_EN_6(r_mux_6.RD_EN),
                .RD_EN_7(r_mux_7.RD_EN),
                .RD_EN_8(r_mux_8.RD_EN),
                .RD_EN_9(r_mux_9.RD_EN),
                .RD_EN_10(r_mux_10.RD_EN),
                .RD_EN_11(r_mux_11.RD_EN),
                .RD_EN_12(r_mux_12.RD_EN),
                .RD_EN_13(r_mux_13.RD_EN),
                .RD_EN_14(r_mux_14.RD_EN),
                .RD_EN_15(r_mux_15.RD_EN),

                .SRAM_NUM_0(SRAM_NUM_0),
                .SRAM_NUM_1(SRAM_NUM_1),
                .SRAM_NUM_2(SRAM_NUM_2),
                .SRAM_NUM_3(SRAM_NUM_3),
                .SRAM_NUM_4(SRAM_NUM_4),
                .SRAM_NUM_5(SRAM_NUM_5),
                .SRAM_NUM_6(SRAM_NUM_6),
                .SRAM_NUM_7(SRAM_NUM_7),
                .SRAM_NUM_8(SRAM_NUM_8),
                .SRAM_NUM_9(SRAM_NUM_9),
                .SRAM_NUM_10(SRAM_NUM_10),
                .SRAM_NUM_11(SRAM_NUM_11),
                .SRAM_NUM_12(SRAM_NUM_12),
                .SRAM_NUM_13(SRAM_NUM_13),
                .SRAM_NUM_14(SRAM_NUM_14),
                .SRAM_NUM_15(SRAM_NUM_15),

                .ADDR_0(SRAM_ADDR_0),
                .ADDR_1(SRAM_ADDR_1),
                .ADDR_2(SRAM_ADDR_2),
                .ADDR_3(SRAM_ADDR_3),
                .ADDR_4(SRAM_ADDR_4),
                .ADDR_5(SRAM_ADDR_5),
                .ADDR_6(SRAM_ADDR_6),
                .ADDR_7(SRAM_ADDR_7),
                .ADDR_8(SRAM_ADDR_8),
                .ADDR_9(SRAM_ADDR_9),
                .ADDR_10(SRAM_ADDR_10),
                .ADDR_11(SRAM_ADDR_11),
                .ADDR_12(SRAM_ADDR_12),
                .ADDR_13(SRAM_ADDR_13),
                .ADDR_14(SRAM_ADDR_14),
                .ADDR_15(SRAM_ADDR_15),
                
                .ADDR_O(ADDR_O_14),
                .RD(RD_14)
            );
rd_sram_ctrl#(.RD_SRAM_num(31))
            rd_sram_ctrl_u_15(
                .RD_EN_0(r_mux_0.RD_EN),
                .RD_EN_1(r_mux_1.RD_EN),
                .RD_EN_2(r_mux_2.RD_EN),
                .RD_EN_3(r_mux_3.RD_EN),
                .RD_EN_4(r_mux_4.RD_EN),
                .RD_EN_5(r_mux_5.RD_EN),
                .RD_EN_6(r_mux_6.RD_EN),
                .RD_EN_7(r_mux_7.RD_EN),
                .RD_EN_8(r_mux_8.RD_EN),
                .RD_EN_9(r_mux_9.RD_EN),
                .RD_EN_10(r_mux_10.RD_EN),
                .RD_EN_11(r_mux_11.RD_EN),
                .RD_EN_12(r_mux_12.RD_EN),
                .RD_EN_13(r_mux_13.RD_EN),
                .RD_EN_14(r_mux_14.RD_EN),
                .RD_EN_15(r_mux_15.RD_EN),

                .SRAM_NUM_0(SRAM_NUM_0),
                .SRAM_NUM_1(SRAM_NUM_1),
                .SRAM_NUM_2(SRAM_NUM_2),
                .SRAM_NUM_3(SRAM_NUM_3),
                .SRAM_NUM_4(SRAM_NUM_4),
                .SRAM_NUM_5(SRAM_NUM_5),
                .SRAM_NUM_6(SRAM_NUM_6),
                .SRAM_NUM_7(SRAM_NUM_7),
                .SRAM_NUM_8(SRAM_NUM_8),
                .SRAM_NUM_9(SRAM_NUM_9),
                .SRAM_NUM_10(SRAM_NUM_10),
                .SRAM_NUM_11(SRAM_NUM_11),
                .SRAM_NUM_12(SRAM_NUM_12),
                .SRAM_NUM_13(SRAM_NUM_13),
                .SRAM_NUM_14(SRAM_NUM_14),
                .SRAM_NUM_15(SRAM_NUM_15),

                .ADDR_0(SRAM_ADDR_0),
                .ADDR_1(SRAM_ADDR_1),
                .ADDR_2(SRAM_ADDR_2),
                .ADDR_3(SRAM_ADDR_3),
                .ADDR_4(SRAM_ADDR_4),
                .ADDR_5(SRAM_ADDR_5),
                .ADDR_6(SRAM_ADDR_6),
                .ADDR_7(SRAM_ADDR_7),
                .ADDR_8(SRAM_ADDR_8),
                .ADDR_9(SRAM_ADDR_9),
                .ADDR_10(SRAM_ADDR_10),
                .ADDR_11(SRAM_ADDR_11),
                .ADDR_12(SRAM_ADDR_12),
                .ADDR_13(SRAM_ADDR_13),
                .ADDR_14(SRAM_ADDR_14),
                .ADDR_15(SRAM_ADDR_15),
                
                .ADDR_O(ADDR_O_15),
                .RD(RD_15)
            );

assign sram_mux_0.RD=RD_0;
assign sram_mux_1.RD=RD_1;
assign sram_mux_2.RD=RD_2;
assign sram_mux_3.RD=RD_3;
assign sram_mux_4.RD=RD_4;
assign sram_mux_5.RD=RD_5;
assign sram_mux_6.RD=RD_6;
assign sram_mux_7.RD=RD_7;
assign sram_mux_8.RD=RD_8;
assign sram_mux_9.RD=RD_9;
assign sram_mux_10.RD=RD_10;
assign sram_mux_11.RD=RD_11;
assign sram_mux_12.RD=RD_12;
assign sram_mux_13.RD=RD_13;
assign sram_mux_14.RD=RD_14;
assign sram_mux_15.RD=RD_15;

assign sram_mux_0.R_ADDR=ADDR_O_0;
assign sram_mux_1.R_ADDR=ADDR_O_1;
assign sram_mux_2.R_ADDR=ADDR_O_2;
assign sram_mux_3.R_ADDR=ADDR_O_3;
assign sram_mux_4.R_ADDR=ADDR_O_4;
assign sram_mux_5.R_ADDR=ADDR_O_5;
assign sram_mux_6.R_ADDR=ADDR_O_6;
assign sram_mux_7.R_ADDR=ADDR_O_7;
assign sram_mux_8.R_ADDR=ADDR_O_8;
assign sram_mux_9.R_ADDR=ADDR_O_9;
assign sram_mux_10.R_ADDR=ADDR_O_10;
assign sram_mux_11.R_ADDR=ADDR_O_11;
assign sram_mux_12.R_ADDR=ADDR_O_12;
assign sram_mux_13.R_ADDR=ADDR_O_13;
assign sram_mux_14.R_ADDR=ADDR_O_14;
assign sram_mux_15.R_ADDR=ADDR_O_15;

always_comb begin
    case(SRAM_NUM_0[3:0]&{4{r_mux_0.RD_EN}})
    4'd0:r_mux_0.RD_DATA=sram_mux_0.R_DATA;
    4'd1:r_mux_0.RD_DATA=sram_mux_1.R_DATA;
    4'd2:r_mux_0.RD_DATA=sram_mux_2.R_DATA;
    4'd3:r_mux_0.RD_DATA=sram_mux_3.R_DATA;
    4'd4:r_mux_0.RD_DATA=sram_mux_4.R_DATA;
    4'd5:r_mux_0.RD_DATA=sram_mux_5.R_DATA;
    4'd6:r_mux_0.RD_DATA=sram_mux_6.R_DATA;
    4'd7:r_mux_0.RD_DATA=sram_mux_7.R_DATA;
    4'd8:r_mux_0.RD_DATA=sram_mux_8.R_DATA;
    4'd9:r_mux_0.RD_DATA=sram_mux_9.R_DATA;
    4'd10:r_mux_0.RD_DATA=sram_mux_10.R_DATA;
    4'd11:r_mux_0.RD_DATA=sram_mux_11.R_DATA;
    4'd12:r_mux_0.RD_DATA=sram_mux_12.R_DATA;
    4'd13:r_mux_0.RD_DATA=sram_mux_13.R_DATA;
    4'd14:r_mux_0.RD_DATA=sram_mux_14.R_DATA;
    4'd15:r_mux_0.RD_DATA=sram_mux_15.R_DATA;
    default: begin
        r_mux_0.RD_DATA=36'd0;
    end
    endcase
end
always_comb begin
    case(SRAM_NUM_1[3:0]&{4{r_mux_1.RD_EN}})
    4'd0:r_mux_1.RD_DATA=sram_mux_0.R_DATA;
    4'd1:r_mux_1.RD_DATA=sram_mux_1.R_DATA;
    4'd2:r_mux_1.RD_DATA=sram_mux_2.R_DATA;
    4'd3:r_mux_1.RD_DATA=sram_mux_3.R_DATA;
    4'd4:r_mux_1.RD_DATA=sram_mux_4.R_DATA;
    4'd5:r_mux_1.RD_DATA=sram_mux_5.R_DATA;
    4'd6:r_mux_1.RD_DATA=sram_mux_6.R_DATA;
    4'd7:r_mux_1.RD_DATA=sram_mux_7.R_DATA;
    4'd8:r_mux_1.RD_DATA=sram_mux_8.R_DATA;
    4'd9:r_mux_1.RD_DATA=sram_mux_9.R_DATA;
    4'd10:r_mux_1.RD_DATA=sram_mux_10.R_DATA;
    4'd11:r_mux_1.RD_DATA=sram_mux_11.R_DATA;
    4'd12:r_mux_1.RD_DATA=sram_mux_12.R_DATA;
    4'd13:r_mux_1.RD_DATA=sram_mux_13.R_DATA;
    4'd14:r_mux_1.RD_DATA=sram_mux_14.R_DATA;
    4'd15:r_mux_1.RD_DATA=sram_mux_15.R_DATA;
    default: begin
        r_mux_1.RD_DATA=36'd0;
    end
    endcase
end
always_comb begin
    case(SRAM_NUM_2[3:0]&{4{r_mux_2.RD_EN}})
    4'd0:r_mux_2.RD_DATA=sram_mux_0.R_DATA;
    4'd1:r_mux_2.RD_DATA=sram_mux_1.R_DATA;
    4'd2:r_mux_2.RD_DATA=sram_mux_2.R_DATA;
    4'd3:r_mux_2.RD_DATA=sram_mux_3.R_DATA;
    4'd4:r_mux_2.RD_DATA=sram_mux_4.R_DATA;
    4'd5:r_mux_2.RD_DATA=sram_mux_5.R_DATA;
    4'd6:r_mux_2.RD_DATA=sram_mux_6.R_DATA;
    4'd7:r_mux_2.RD_DATA=sram_mux_7.R_DATA;
    4'd8:r_mux_2.RD_DATA=sram_mux_8.R_DATA;
    4'd9:r_mux_2.RD_DATA=sram_mux_9.R_DATA;
    4'd10:r_mux_2.RD_DATA=sram_mux_10.R_DATA;
    4'd11:r_mux_2.RD_DATA=sram_mux_11.R_DATA;
    4'd12:r_mux_2.RD_DATA=sram_mux_12.R_DATA;
    4'd13:r_mux_2.RD_DATA=sram_mux_13.R_DATA;
    4'd14:r_mux_2.RD_DATA=sram_mux_14.R_DATA;
    4'd15:r_mux_2.RD_DATA=sram_mux_15.R_DATA;
    default: begin
        r_mux_2.RD_DATA=36'd0;
    end
    endcase
end
always_comb begin
    case(SRAM_NUM_3[3:0]&{4{r_mux_3.RD_EN}})
    4'd0:r_mux_3.RD_DATA=sram_mux_0.R_DATA;
    4'd1:r_mux_3.RD_DATA=sram_mux_1.R_DATA;
    4'd2:r_mux_3.RD_DATA=sram_mux_2.R_DATA;
    4'd3:r_mux_3.RD_DATA=sram_mux_3.R_DATA;
    4'd4:r_mux_3.RD_DATA=sram_mux_4.R_DATA;
    4'd5:r_mux_3.RD_DATA=sram_mux_5.R_DATA;
    4'd6:r_mux_3.RD_DATA=sram_mux_6.R_DATA;
    4'd7:r_mux_3.RD_DATA=sram_mux_7.R_DATA;
    4'd8:r_mux_3.RD_DATA=sram_mux_8.R_DATA;
    4'd9:r_mux_3.RD_DATA=sram_mux_9.R_DATA;
    4'd10:r_mux_3.RD_DATA=sram_mux_10.R_DATA;
    4'd11:r_mux_3.RD_DATA=sram_mux_11.R_DATA;
    4'd12:r_mux_3.RD_DATA=sram_mux_12.R_DATA;
    4'd13:r_mux_3.RD_DATA=sram_mux_13.R_DATA;
    4'd14:r_mux_3.RD_DATA=sram_mux_14.R_DATA;
    4'd15:r_mux_3.RD_DATA=sram_mux_15.R_DATA;
    default: begin
        r_mux_3.RD_DATA=36'd0;
    end
    endcase
end
always_comb begin
    case(SRAM_NUM_4[3:0]&{4{r_mux_4.RD_EN}})
    4'd0:r_mux_4.RD_DATA=sram_mux_0.R_DATA;
    4'd1:r_mux_4.RD_DATA=sram_mux_1.R_DATA;
    4'd2:r_mux_4.RD_DATA=sram_mux_2.R_DATA;
    4'd3:r_mux_4.RD_DATA=sram_mux_3.R_DATA;
    4'd4:r_mux_4.RD_DATA=sram_mux_4.R_DATA;
    4'd5:r_mux_4.RD_DATA=sram_mux_5.R_DATA;
    4'd6:r_mux_4.RD_DATA=sram_mux_6.R_DATA;
    4'd7:r_mux_4.RD_DATA=sram_mux_7.R_DATA;
    4'd8:r_mux_4.RD_DATA=sram_mux_8.R_DATA;
    4'd9:r_mux_4.RD_DATA=sram_mux_9.R_DATA;
    4'd10:r_mux_4.RD_DATA=sram_mux_10.R_DATA;
    4'd11:r_mux_4.RD_DATA=sram_mux_11.R_DATA;
    4'd12:r_mux_4.RD_DATA=sram_mux_12.R_DATA;
    4'd13:r_mux_4.RD_DATA=sram_mux_13.R_DATA;
    4'd14:r_mux_4.RD_DATA=sram_mux_14.R_DATA;
    4'd15:r_mux_4.RD_DATA=sram_mux_15.R_DATA;
    default: begin
        r_mux_4.RD_DATA=36'd0;
    end
    endcase
end
always_comb begin
    case(SRAM_NUM_5[3:0]&{4{r_mux_5.RD_EN}})
    4'd0:r_mux_5.RD_DATA=sram_mux_0.R_DATA;
    4'd1:r_mux_5.RD_DATA=sram_mux_1.R_DATA;
    4'd2:r_mux_5.RD_DATA=sram_mux_2.R_DATA;
    4'd3:r_mux_5.RD_DATA=sram_mux_3.R_DATA;
    4'd4:r_mux_5.RD_DATA=sram_mux_4.R_DATA;
    4'd5:r_mux_5.RD_DATA=sram_mux_5.R_DATA;
    4'd6:r_mux_5.RD_DATA=sram_mux_6.R_DATA;
    4'd7:r_mux_5.RD_DATA=sram_mux_7.R_DATA;
    4'd8:r_mux_5.RD_DATA=sram_mux_8.R_DATA;
    4'd9:r_mux_5.RD_DATA=sram_mux_9.R_DATA;
    4'd10:r_mux_5.RD_DATA=sram_mux_10.R_DATA;
    4'd11:r_mux_5.RD_DATA=sram_mux_11.R_DATA;
    4'd12:r_mux_5.RD_DATA=sram_mux_12.R_DATA;
    4'd13:r_mux_5.RD_DATA=sram_mux_13.R_DATA;
    4'd14:r_mux_5.RD_DATA=sram_mux_14.R_DATA;
    4'd15:r_mux_5.RD_DATA=sram_mux_15.R_DATA;
    default: begin
        r_mux_5.RD_DATA=36'd0;
    end
    endcase
end
always_comb begin
    case(SRAM_NUM_6[3:0]&{4{r_mux_6.RD_EN}})
    4'd0:r_mux_6.RD_DATA=sram_mux_0.R_DATA;
    4'd1:r_mux_6.RD_DATA=sram_mux_1.R_DATA;
    4'd2:r_mux_6.RD_DATA=sram_mux_2.R_DATA;
    4'd3:r_mux_6.RD_DATA=sram_mux_3.R_DATA;
    4'd4:r_mux_6.RD_DATA=sram_mux_4.R_DATA;
    4'd5:r_mux_6.RD_DATA=sram_mux_5.R_DATA;
    4'd6:r_mux_6.RD_DATA=sram_mux_6.R_DATA;
    4'd7:r_mux_6.RD_DATA=sram_mux_7.R_DATA;
    4'd8:r_mux_6.RD_DATA=sram_mux_8.R_DATA;
    4'd9:r_mux_6.RD_DATA=sram_mux_9.R_DATA;
    4'd10:r_mux_6.RD_DATA=sram_mux_10.R_DATA;
    4'd11:r_mux_6.RD_DATA=sram_mux_11.R_DATA;
    4'd12:r_mux_6.RD_DATA=sram_mux_12.R_DATA;
    4'd13:r_mux_6.RD_DATA=sram_mux_13.R_DATA;
    4'd14:r_mux_6.RD_DATA=sram_mux_14.R_DATA;
    4'd15:r_mux_6.RD_DATA=sram_mux_15.R_DATA;
    default: begin
        r_mux_6.RD_DATA=36'd0;
    end
    endcase
end
always_comb begin
    case(SRAM_NUM_7[3:0]&{4{r_mux_7.RD_EN}})
    4'd0:r_mux_7.RD_DATA=sram_mux_0.R_DATA;
    4'd1:r_mux_7.RD_DATA=sram_mux_1.R_DATA;
    4'd2:r_mux_7.RD_DATA=sram_mux_2.R_DATA;
    4'd3:r_mux_7.RD_DATA=sram_mux_3.R_DATA;
    4'd4:r_mux_7.RD_DATA=sram_mux_4.R_DATA;
    4'd5:r_mux_7.RD_DATA=sram_mux_5.R_DATA;
    4'd6:r_mux_7.RD_DATA=sram_mux_6.R_DATA;
    4'd7:r_mux_7.RD_DATA=sram_mux_7.R_DATA;
    4'd8:r_mux_7.RD_DATA=sram_mux_8.R_DATA;
    4'd9:r_mux_7.RD_DATA=sram_mux_9.R_DATA;
    4'd10:r_mux_7.RD_DATA=sram_mux_10.R_DATA;
    4'd11:r_mux_7.RD_DATA=sram_mux_11.R_DATA;
    4'd12:r_mux_7.RD_DATA=sram_mux_12.R_DATA;
    4'd13:r_mux_7.RD_DATA=sram_mux_13.R_DATA;
    4'd14:r_mux_7.RD_DATA=sram_mux_14.R_DATA;
    4'd15:r_mux_7.RD_DATA=sram_mux_15.R_DATA;
    default: begin
        r_mux_7.RD_DATA=36'd0;
    end
    endcase
end
always_comb begin
    case(SRAM_NUM_8[3:0]&{4{r_mux_8.RD_EN}})
    4'd0:r_mux_8.RD_DATA=sram_mux_0.R_DATA;
    4'd1:r_mux_8.RD_DATA=sram_mux_1.R_DATA;
    4'd2:r_mux_8.RD_DATA=sram_mux_2.R_DATA;
    4'd3:r_mux_8.RD_DATA=sram_mux_3.R_DATA;
    4'd4:r_mux_8.RD_DATA=sram_mux_4.R_DATA;
    4'd5:r_mux_8.RD_DATA=sram_mux_5.R_DATA;
    4'd6:r_mux_8.RD_DATA=sram_mux_6.R_DATA;
    4'd7:r_mux_8.RD_DATA=sram_mux_7.R_DATA;
    4'd8:r_mux_8.RD_DATA=sram_mux_8.R_DATA;
    4'd9:r_mux_8.RD_DATA=sram_mux_9.R_DATA;
    4'd10:r_mux_8.RD_DATA=sram_mux_10.R_DATA;
    4'd11:r_mux_8.RD_DATA=sram_mux_11.R_DATA;
    4'd12:r_mux_8.RD_DATA=sram_mux_12.R_DATA;
    4'd13:r_mux_8.RD_DATA=sram_mux_13.R_DATA;
    4'd14:r_mux_8.RD_DATA=sram_mux_14.R_DATA;
    4'd15:r_mux_8.RD_DATA=sram_mux_15.R_DATA;
    default: begin
        r_mux_8.RD_DATA=36'd0;
    end
    endcase
end
always_comb begin
    case(SRAM_NUM_9[3:0]&{4{r_mux_9.RD_EN}})
    4'd0:r_mux_9.RD_DATA=sram_mux_0.R_DATA;
    4'd1:r_mux_9.RD_DATA=sram_mux_1.R_DATA;
    4'd2:r_mux_9.RD_DATA=sram_mux_2.R_DATA;
    4'd3:r_mux_9.RD_DATA=sram_mux_3.R_DATA;
    4'd4:r_mux_9.RD_DATA=sram_mux_4.R_DATA;
    4'd5:r_mux_9.RD_DATA=sram_mux_5.R_DATA;
    4'd6:r_mux_9.RD_DATA=sram_mux_6.R_DATA;
    4'd7:r_mux_9.RD_DATA=sram_mux_7.R_DATA;
    4'd8:r_mux_9.RD_DATA=sram_mux_8.R_DATA;
    4'd9:r_mux_9.RD_DATA=sram_mux_9.R_DATA;
    4'd10:r_mux_9.RD_DATA=sram_mux_10.R_DATA;
    4'd11:r_mux_9.RD_DATA=sram_mux_11.R_DATA;
    4'd12:r_mux_9.RD_DATA=sram_mux_12.R_DATA;
    4'd13:r_mux_9.RD_DATA=sram_mux_13.R_DATA;
    4'd14:r_mux_9.RD_DATA=sram_mux_14.R_DATA;
    4'd15:r_mux_9.RD_DATA=sram_mux_15.R_DATA;
    default: begin
        r_mux_9.RD_DATA=36'd0;
    end
    endcase
end
always_comb begin
    case(SRAM_NUM_10[3:0]&{4{r_mux_10.RD_EN}})
    4'd0:r_mux_10.RD_DATA=sram_mux_0.R_DATA;
    4'd1:r_mux_10.RD_DATA=sram_mux_1.R_DATA;
    4'd2:r_mux_10.RD_DATA=sram_mux_2.R_DATA;
    4'd3:r_mux_10.RD_DATA=sram_mux_3.R_DATA;
    4'd4:r_mux_10.RD_DATA=sram_mux_4.R_DATA;
    4'd5:r_mux_10.RD_DATA=sram_mux_5.R_DATA;
    4'd6:r_mux_10.RD_DATA=sram_mux_6.R_DATA;
    4'd7:r_mux_10.RD_DATA=sram_mux_7.R_DATA;
    4'd8:r_mux_10.RD_DATA=sram_mux_8.R_DATA;
    4'd9:r_mux_10.RD_DATA=sram_mux_9.R_DATA;
    4'd10:r_mux_10.RD_DATA=sram_mux_10.R_DATA;
    4'd11:r_mux_10.RD_DATA=sram_mux_11.R_DATA;
    4'd12:r_mux_10.RD_DATA=sram_mux_12.R_DATA;
    4'd13:r_mux_10.RD_DATA=sram_mux_13.R_DATA;
    4'd14:r_mux_10.RD_DATA=sram_mux_14.R_DATA;
    4'd15:r_mux_10.RD_DATA=sram_mux_15.R_DATA;
    default: begin
        r_mux_10.RD_DATA=36'd0;
    end
    endcase
end
always_comb begin
    case(SRAM_NUM_11[3:0]&{4{r_mux_11.RD_EN}})
    4'd0:r_mux_11.RD_DATA=sram_mux_0.R_DATA;
    4'd1:r_mux_11.RD_DATA=sram_mux_1.R_DATA;
    4'd2:r_mux_11.RD_DATA=sram_mux_2.R_DATA;
    4'd3:r_mux_11.RD_DATA=sram_mux_3.R_DATA;
    4'd4:r_mux_11.RD_DATA=sram_mux_4.R_DATA;
    4'd5:r_mux_11.RD_DATA=sram_mux_5.R_DATA;
    4'd6:r_mux_11.RD_DATA=sram_mux_6.R_DATA;
    4'd7:r_mux_11.RD_DATA=sram_mux_7.R_DATA;
    4'd8:r_mux_11.RD_DATA=sram_mux_8.R_DATA;
    4'd9:r_mux_11.RD_DATA=sram_mux_9.R_DATA;
    4'd10:r_mux_11.RD_DATA=sram_mux_10.R_DATA;
    4'd11:r_mux_11.RD_DATA=sram_mux_11.R_DATA;
    4'd12:r_mux_11.RD_DATA=sram_mux_12.R_DATA;
    4'd13:r_mux_11.RD_DATA=sram_mux_13.R_DATA;
    4'd14:r_mux_11.RD_DATA=sram_mux_14.R_DATA;
    4'd15:r_mux_11.RD_DATA=sram_mux_15.R_DATA;
    default: begin
        r_mux_11.RD_DATA=36'd0;
    end
    endcase
end
always_comb begin
    case(SRAM_NUM_12[3:0]&{4{r_mux_12.RD_EN}})
    4'd0:r_mux_12.RD_DATA=sram_mux_0.R_DATA;
    4'd1:r_mux_12.RD_DATA=sram_mux_1.R_DATA;
    4'd2:r_mux_12.RD_DATA=sram_mux_2.R_DATA;
    4'd3:r_mux_12.RD_DATA=sram_mux_3.R_DATA;
    4'd4:r_mux_12.RD_DATA=sram_mux_4.R_DATA;
    4'd5:r_mux_12.RD_DATA=sram_mux_5.R_DATA;
    4'd6:r_mux_12.RD_DATA=sram_mux_6.R_DATA;
    4'd7:r_mux_12.RD_DATA=sram_mux_7.R_DATA;
    4'd8:r_mux_12.RD_DATA=sram_mux_8.R_DATA;
    4'd9:r_mux_12.RD_DATA=sram_mux_9.R_DATA;
    4'd10:r_mux_12.RD_DATA=sram_mux_10.R_DATA;
    4'd11:r_mux_12.RD_DATA=sram_mux_11.R_DATA;
    4'd12:r_mux_12.RD_DATA=sram_mux_12.R_DATA;
    4'd13:r_mux_12.RD_DATA=sram_mux_13.R_DATA;
    4'd14:r_mux_12.RD_DATA=sram_mux_14.R_DATA;
    4'd15:r_mux_12.RD_DATA=sram_mux_15.R_DATA;
    default: begin
        r_mux_12.RD_DATA=36'd0;
    end
    endcase
end
always_comb begin
    case(SRAM_NUM_13[3:0]&{4{r_mux_13.RD_EN}})
    4'd0:r_mux_13.RD_DATA=sram_mux_0.R_DATA;
    4'd1:r_mux_13.RD_DATA=sram_mux_1.R_DATA;
    4'd2:r_mux_13.RD_DATA=sram_mux_2.R_DATA;
    4'd3:r_mux_13.RD_DATA=sram_mux_3.R_DATA;
    4'd4:r_mux_13.RD_DATA=sram_mux_4.R_DATA;
    4'd5:r_mux_13.RD_DATA=sram_mux_5.R_DATA;
    4'd6:r_mux_13.RD_DATA=sram_mux_6.R_DATA;
    4'd7:r_mux_13.RD_DATA=sram_mux_7.R_DATA;
    4'd8:r_mux_13.RD_DATA=sram_mux_8.R_DATA;
    4'd9:r_mux_13.RD_DATA=sram_mux_9.R_DATA;
    4'd10:r_mux_13.RD_DATA=sram_mux_10.R_DATA;
    4'd11:r_mux_13.RD_DATA=sram_mux_11.R_DATA;
    4'd12:r_mux_13.RD_DATA=sram_mux_12.R_DATA;
    4'd13:r_mux_13.RD_DATA=sram_mux_13.R_DATA;
    4'd14:r_mux_13.RD_DATA=sram_mux_14.R_DATA;
    4'd15:r_mux_13.RD_DATA=sram_mux_15.R_DATA;
    default: begin
        r_mux_13.RD_DATA=36'd0;
    end
    endcase
end
always_comb begin
    case(SRAM_NUM_14[3:0]&{4{r_mux_14.RD_EN}})
    4'd0:r_mux_14.RD_DATA=sram_mux_0.R_DATA;
    4'd1:r_mux_14.RD_DATA=sram_mux_1.R_DATA;
    4'd2:r_mux_14.RD_DATA=sram_mux_2.R_DATA;
    4'd3:r_mux_14.RD_DATA=sram_mux_3.R_DATA;
    4'd4:r_mux_14.RD_DATA=sram_mux_4.R_DATA;
    4'd5:r_mux_14.RD_DATA=sram_mux_5.R_DATA;
    4'd6:r_mux_14.RD_DATA=sram_mux_6.R_DATA;
    4'd7:r_mux_14.RD_DATA=sram_mux_7.R_DATA;
    4'd8:r_mux_14.RD_DATA=sram_mux_8.R_DATA;
    4'd9:r_mux_14.RD_DATA=sram_mux_9.R_DATA;
    4'd10:r_mux_14.RD_DATA=sram_mux_10.R_DATA;
    4'd11:r_mux_14.RD_DATA=sram_mux_11.R_DATA;
    4'd12:r_mux_14.RD_DATA=sram_mux_12.R_DATA;
    4'd13:r_mux_14.RD_DATA=sram_mux_13.R_DATA;
    4'd14:r_mux_14.RD_DATA=sram_mux_14.R_DATA;
    4'd15:r_mux_14.RD_DATA=sram_mux_15.R_DATA;
    default: begin
        r_mux_14.RD_DATA=36'd0;
    end
    endcase
end
always_comb begin
    case(SRAM_NUM_15[3:0]&{4{r_mux_15.RD_EN}})
    4'd0:r_mux_15.RD_DATA=sram_mux_0.R_DATA;
    4'd1:r_mux_15.RD_DATA=sram_mux_1.R_DATA;
    4'd2:r_mux_15.RD_DATA=sram_mux_2.R_DATA;
    4'd3:r_mux_15.RD_DATA=sram_mux_3.R_DATA;
    4'd4:r_mux_15.RD_DATA=sram_mux_4.R_DATA;
    4'd5:r_mux_15.RD_DATA=sram_mux_5.R_DATA;
    4'd6:r_mux_15.RD_DATA=sram_mux_6.R_DATA;
    4'd7:r_mux_15.RD_DATA=sram_mux_7.R_DATA;
    4'd8:r_mux_15.RD_DATA=sram_mux_8.R_DATA;
    4'd9:r_mux_15.RD_DATA=sram_mux_9.R_DATA;
    4'd10:r_mux_15.RD_DATA=sram_mux_10.R_DATA;
    4'd11:r_mux_15.RD_DATA=sram_mux_11.R_DATA;
    4'd12:r_mux_15.RD_DATA=sram_mux_12.R_DATA;
    4'd13:r_mux_15.RD_DATA=sram_mux_13.R_DATA;
    4'd14:r_mux_15.RD_DATA=sram_mux_14.R_DATA;
    4'd15:r_mux_15.RD_DATA=sram_mux_15.R_DATA;
    default: begin
        r_mux_15.RD_DATA=36'd0;
    end
    endcase
end

assign r_mux_0.RD_DATA_VLD=r_mux_0.RD_EN;
assign r_mux_1.RD_DATA_VLD=r_mux_1.RD_EN;
assign r_mux_2.RD_DATA_VLD=r_mux_2.RD_EN;
assign r_mux_3.RD_DATA_VLD=r_mux_3.RD_EN;
assign r_mux_4.RD_DATA_VLD=r_mux_4.RD_EN;
assign r_mux_5.RD_DATA_VLD=r_mux_5.RD_EN;
assign r_mux_6.RD_DATA_VLD=r_mux_6.RD_EN;
assign r_mux_7.RD_DATA_VLD=r_mux_7.RD_EN;
assign r_mux_8.RD_DATA_VLD=r_mux_8.RD_EN;
assign r_mux_9.RD_DATA_VLD=r_mux_9.RD_EN;
assign r_mux_10.RD_DATA_VLD=r_mux_10.RD_EN;
assign r_mux_11.RD_DATA_VLD=r_mux_11.RD_EN;
assign r_mux_12.RD_DATA_VLD=r_mux_12.RD_EN;
assign r_mux_13.RD_DATA_VLD=r_mux_13.RD_EN;
assign r_mux_14.RD_DATA_VLD=r_mux_14.RD_EN;
assign r_mux_15.RD_DATA_VLD=r_mux_15.RD_EN;

endmodule

